Abstract: Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of NO activation of an oxide surface. Once activated, a fluorine-containing gas or vapor etches the activated surface. Etching is self-limiting as once the activated surface is removed, etching stops since the fluorine species does not spontaneously react with the un-activated oxide surface. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where accurate removal of one or multiple atomic layers of material is desired.

Abstract: The embodiments herein relate to methods and apparatus for performing ion etching on a semiconductor substrate, as well as methods for forming such apparatus. In some embodiments, an electrode assembly may be fabricated, the electrode assembly including a plurality of electrodes having different purposes, with each electrode secured to the next in a mechanically stable manner. Apertures may be formed in each electrode after the electrodes are secured together, thereby ensuring that the apertures are well-aligned between neighboring electrodes. In some cases, the electrodes are made from degeneratively doped silicon, and the electrode assembly is secured together through electrostatic bonding. Other electrode materials and methods of securing may also be used. The electrode assembly may include a hollow cathode emitter electrode in some cases, which may have a frustoconical or other non-cylindrical aperture shape. A chamber liner and/or reflector may also be present in some cases.

Abstract: Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of NO activation of an oxide surface. Once activated, a fluorine-containing gas or vapor etches the activated surface. Etching is self-limiting as once the activated surface is removed, etching stops since the fluorine species does not spontaneously react with the un-activated oxide surface. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where accurate removal of one or multiple atomic layers of material is desired.

Abstract: Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of a reaction of anhydrous HF with an activated surface of an oxide, with an emphasis on removal of water generated in the reaction. In certain embodiments the oxide surface is first modified by adsorbing an OH-containing species (e.g., an alcohol) or by forming OH bonds using a hydrogen-containing plasma. The activated oxide is then etched by a separately introduced anhydrous HF, while the water generated in the reaction is removed from the surface of the substrate as the reaction proceeds, or at any time during or after the reaction. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where accurate removal of one or multiple atomic layers of material is desired.

Abstract: Methods of selectively etching silicon nitride are provided. Silicon nitride layers are exposed to a fluorinating gas and nitric oxide (NO), which may be formed by reacting nitrous oxide (N2O) and oxygen (O2) in a plasma. Methods also include defluorinating the substrate prior to turning off the plasma to increase etch selectivity of silicon nitride.

Abstract: Various embodiments herein relate to methods and apparatus for performing anisotropic ion beam etching to form arrays of channels. The channels may be formed in semiconductor material, and may be used in a gate-all-around device. Generally speaking, a patterned mask layer is provided over a layer of semiconductor material. Ions are directed toward the substrate while the substrate is positioned in two particular orientations with respect to the ion trajectory. The substrate switches between these orientations such that ions impinge upon the substrate from two opposite angles. The patterned mask layer shadows/protects the underlying semiconductor material such that the channels are formed in intersecting shadowed regions.

Abstract: A device for processing wafer-shaped articles comprises a closed process chamber that provides a gas-tight enclosure. A rotary chuck is located within the closed process chamber. A heater is positioned relative to the chuck so as to heat a wafer shaped article held on the chuck from one side only and without contacting the wafer shaped article. The heater emits radiation having a maximum intensity in a wavelength range from 390 nm to 550 nm. At least one first liquid dispenser is positioned relative to the chuck so as to dispense a process liquid onto a side of a wafer shaped article that is opposite the side of the wafer-shaped article facing the heater.

Abstract: Various embodiments herein relate to methods and apparatus for etching feature on a substrate. In a number of embodiments, no substrate rotation or tilting is used. While conventional etching processes rely on substrate rotation to even out the distribution of ions over the substrate surface, various embodiments herein achieve this purpose by moving the ion beams relative to the ion source. Movement of the ion beams can be achieved in a number of ways including electrostatic techniques, mechanical techniques, magnetic techniques, and combinations thereof.

Abstract: The embodiments herein relate to methods and apparatus for performing ion etching on a semiconductor substrate, as well as methods for forming such apparatus. In some embodiments, an electrode assembly may be fabricated, the electrode assembly including a plurality of electrodes having different purposes, with each electrode secured to the next in a mechanically stable manner. Apertures may be formed in each electrode after the electrodes are secured together, thereby ensuring that the apertures are well-aligned between neighboring electrodes. In some cases, the electrodes are made from degeneratively doped silicon, and the electrode assembly is secured together through electrostatic bonding. Other electrode materials and methods of securing may also be used. The electrode assembly may include a hollow cathode emitter electrode in some cases, which may have a frustoconical or other non-cylindrical aperture shape. A chamber liner and/or reflector may also be present in some cases.

Abstract: One process that may be used to remove material from a surface is ion etching. In certain cases, ion etching involves delivery of both ions and a reactive gas to a substrate. The disclosed embodiments permit local high pressure delivery of reactive gas to a substrate while maintaining a much lower pressure on portions of the substrate that are outside of the local high pressure delivery area. The low pressure is achieved by confining the high pressure reactant delivery to a small area and vacuuming away excess reactants and byproducts as they leave this small area and before they enter the larger substrate processing region. The disclosed techniques may be used to increase throughput while minimizing deleterious collisions between ions and other species present in the substrate processing region.

Abstract: Systems and methods for processing a substrate include exposing a substrate to UV light from a UV light source having a predetermined wavelength range. The substrate includes a photoresist layer that has been bombarded with ions. The method includes controlling a temperature of the substrate, while exposing the substrate to the UV light, to a temperature less than or equal to a first temperature. The method includes removing the photoresist layer using plasma while maintaining a temperature of the substrate to less than or equal to a strip process temperature after exposing the substrate to the UV light.

Abstract: A fluid distribution member assembly for use in a substrate processing system includes a fluid distribution member having a central portion and a perimeter portion. The fluid distribution member defines at least one slot formed there-through and the at least one slot extends along a non-radial path configured to allow the central portion to expand and rotate with respect to the perimeter portion.

Abstract: A plasma ashing process for removing photoresist, polymers and/or residues from a substrate, the process includes placing the substrate including the photoresist, polymers, and/or residues into a reaction chamber; generating a plasma from a gas mixture comprising oxygen gas (02) and/or an oxygen containing gas; suppressing and/or reducing fast diffusing species in the plasma by adding an atomic oxygen scavenging gas to the gas mixture; and exposing the substrate to the plasma to selectively remove the photoresist, polymers, and/or residues from the substrate, wherein the plasma is substantially free from fast diffusing species.

Abstract: A fluid distribution member assembly for use in a substrate processing system includes a fluid distribution member having a central portion and a perimeter portion. The fluid distribution member defines at least one slot formed there-through and the at least one slot extends along a non-radial path configured to allow the central portion to expand and rotate with respect to the perimeter portion.

Abstract: A method of doping a semiconductor body is provided herein. In one embodiment, a semiconductor body is exposed to an activated hydrogen gas for a predetermined time period and temperature. The activated hydrogen gas that is configured to react with a surface of a semiconductor body. The activated hydrogen gas breaks existing bonds in the substrate (e.g., silicon-silicon bonds), thereby forming a reactive layer comprising weakened (e.g., silicon-hydrogen (Si—H) bonds, silanol (Si—OH) bonds) and/or dangling bonds (e.g., dangling silicon bonds). The dangling bonds, in addition to the easily broken weakened bonds, comprise reactive sites that extend into one or more surfaces of the semiconductor body. A reactant (e.g., n-type dopant, p-type dopant) may then be introduced to contact the reactive layer of the semiconductor body. The reactant chemically bonds to reactive sites comprised within the reactive layer, thereby resulting in a doped layer within the semiconductor body comprising the reactant.

Abstract: A plasma ashing process for removing photoresist, polymers and/or residues from a substrate comprises placing the substrate including the photoresist, polymers, and/or residues into a reaction chamber; generating a plasma from a gas mixture comprising oxygen gas (O2) and/or an oxygen containing gas; suppressing and/or reducing fast diffusing species in the plasma; and exposing the substrate to the plasma to selectively remove the photoresist, polymers, and/or residues from the substrate, wherein the plasma is substantially free from fast diffusing species.

Abstract: An apparatus for treating a workpiece, the apparatus comprising a first chamber configured to treat the workpiece at an elevated temperature, the first chamber including an opening for receiving the workpiece; a second chamber in operative communication with the first chamber, the second chamber including an opening for transferring the workpiece to and from the first chamber, wherein the first chamber opening is aligned with the second chamber opening, and wherein a selected one of the first and the second chambers comprises a gate valve configured to selectively open and close access to the first and second chamber openings; and a thermal isolation plate formed of a material effective to substantially prevent heat transfer from the first chamber to the second chamber, wherein the thermal isolation plate is disposed about the first and second chamber openings in a sealing relationship.

Abstract: A system and methods are provided for mitigating or removing workpiece surface contaminants or conditions. Methods of the invention provide treatment of the wafer surface to provide a known surface condition. The surface condition can then be maintained during and following implantation of the workpiece surface with a dopant.

Abstract: A method of doping a semiconductor body is provided herein. In one embodiment, a semiconductor body is exposed to an activated hydrogen gas for a predetermined time period and temperature. The activated hydrogen gas that is configured to react with a surface of a semiconductor body. The activated hydrogen gas breaks existing bonds in the substrate (e.g., silicon-silicon bonds), thereby forming a reactive layer comprising weakened (e.g., silicon-hydrogen (Si—H) bonds, silanol (Si—OH) bonds) and/or dangling bonds (e.g., dangling silicon bonds). The dangling bonds, in addition to the easily broken weakened bonds, comprise reactive sites that extend into one or more surfaces of the semiconductor body. A reactant (e.g., n-type dopant, p-type dopant) may then be introduced to contact the reactive layer of the semiconductor body. The reactant chemically bonds to reactive sites comprised within the reactive layer, thereby resulting in a doped layer within the semiconductor body comprising the reactant.

Abstract: A system and methods are provided for mitigating or removing workpiece surface contaminants or conditions. Methods of the invention provide treatment of the wafer surface to provide a known surface condition. The surface condition can then be maintained during and following implantation of the workpiece surface with a dopant.