Abstract: Multiple sequential processes are conducted in situ in a single-wafer processing chamber, particularly for forming ultrathin dielectric stacks of high quality. The chamber exhibits single-pass, laminar gas flow, facilitating safe and clean sequential processing. Furthermore, a remote plasma source widens process windows, permitting isothermal sequential processing and thereby reducing the transition time for temperature ramping between in situ steps. In exemplary processes, extremely thin interfacial silicon oxide, nitride and/or oxynitride is grown, followed by in situ silicon nitride deposition. Cleaning, anneal and electrode deposition can also be conducted in situ, reducing transition time without commensurate loss in reaction rates.

Abstract: Described herein is a process chamber with a substantially all-quartz interior surface. The preferred embodiments have upper and lower walls being curved in both the x-z and y-z planes. In one embodiment, the chamber has thin upper and lower dome walls made from a generally transparent material such as quartz, each with a convex exterior surface and a concave interior surface. These walls are joined at their side edges to a cylindrical side wall, preferably formed from a generally translucent material such as bubble quartz. The upper and lower walls and the side wall substantially enclose an all-quartz interior surface, except for apertures used for gas inlet and outlet, wafer intrusion and extraction and wafer retention. An internal reinforcement extends along the entire interior perimeter of the chamber to provide additional strength and support to the chamber. An external reinforcement surrounds the cylindrical side wall to confine outward expansion of the chamber.

Abstract: A method is disclosed for forming an ultrathin oxide layer of uniform thickness. The method is particularly advantageous for producing uniformly thin interfacial oxides beneath materials of high dielectric permitivity, or uniformly thin passivation oxides. Hydrofluoric (HF) etching of a silicon surface, for example, is followed by termination of the silicon surface with ligands larger than H or F, particularly hydroxyl, alkoxy or carboxylic tails. The substrate is oxidized with the surface termination in place. The surface termination and relatively low temperatures moderate the rate of oxidation, such that a controllable thickness of oxide is formed. In some embodiments, the ligand termination is replaced with OH prior to further deposition. The deposition preferably includes alternating, self-limiting chemistries in an atomic layer deposition process, though any other suitable deposition process can be used.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.

Abstract: Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.

Abstract: A substrate to be processed in a high temperature processing chamber is preheated to avoid the problems associated with thermal shock when the substrate is dropped onto a heated susceptor. Preheating is effected by holding the substrate over a susceptor maintained at or near the processing temperature until the temperature of the substrate approaches the processing temperature. Thus, wafer warping and breakage are greatly reduced, and wafer throughput is improved because of time saved in maintaining the susceptor at constant temperature without cool down and reheat periods.

Abstract: Improvements in the design of a low mass wafer holder are disclosed. The improvements include the use of peripherally located, integral lips to space a wafer or other substrate above the base plate of the wafer holder. A uniform gap is thus provided between the wafer and the base plate, such as will temper rapid heat exchanges, allow gas to flow between the wafer and wafer holder during wafer pick-up, and keep the wafer holder thermally coupled with the wafer. At the same time, thermal disturbance from lip contact with the wafer is reduced. Gas flow during pick-up can be provided through radial channels in a wafer holder upper surface, or through backside gas passages. A thicker ring is provided at the wafer holder perimeter, and is provided in some embodiments as an independent piece to accommodate stresses accompanying thermal gradients. Self-centering mechanisms are provided to keep the wafer holder centered relative to a spider which is subject to differential thermal expansion.

Abstract: Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.

Abstract: An improved apparatus and method for substrate layer deposition in which substrate layers are grown by carrier gas delivery of sequential pulses of reactants to the substrate surface. At least one of the reactants comprises excited species, e.g., radicals. In a specific embodiment, the apparatus of this invention provides sequential repeated pulses of reactants in a flow of carrier gas for reaction at a substrate surface. The reactant pulses are delivered with sufficient intervening delay times to minimize undesirable reaction between reactants in adjacent pulses in the gas phase or undesired uncontrolled reactions on the substrate surface.

Abstract: A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no more than about a monolayer of material, capable of completely filling high aspect ratio trenches. Additionally, the trench-fill material composition can be tailored by processes described herein, particularly to match the coefficient of thermal expansion (CTE) to that of the surrounding substrate within which the trench is formed. Mixed phases of mullite and silica have been found to meet the goals of device isolation and matched CTE. The described process includes mixing atomic layer deposition cycles of aluminum oxide and silicon oxide in ratios selected to achieve the desired composition of the isolation material, namely on the order of 30% alumina and 70% silicon oxide by weight.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: Thin, smooth silicon-containing films are prepared by deposition methods that utilize a silicon-containing precursor. In preferred embodiments, the methods result in Si-containing films that are continuous and have a thickness of about 150 Åor less, a surface roughness of about 5 Å rms or less, and a thickness non-uniformity of about 20% or less. Preferred silicon-containing films display a high degree of compositional uniformity when doped or alloyed with other elements. Preferred deposition methods provide improved manufacturing efficiency and can be used to make various useful structures such as wetting layers, HSG silicon, quantum dots, dielectric layers, anti-reflective coatings (ARC"s), gate electrodes and diffusion sources.

Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.

Abstract: A method is disclosed for forming an ultrathin oxide layer of uniform thickness. The method is particularly advantageous for producing uniformly thin interfacial oxides beneath materials of high dielectric permittivity, or uniformly thin passivation oxides. Hydrofluoric (HF) etching of a silicon surface, for example, is followed by termination of the silicon surface with ligands larger than H or F, particularly hydroxyl, alkoxy or carboxylic tails. The substrate is oxidized with the surface termination in place. The surface termination and relatively low temperatures moderate the rate of oxidation, such that a controllable thickness of oxide is formed. In some embodiments, the ligand termination is replaced with OH prior to further deposition. The deposition preferably includes alternating, self-limiting chemistries in an atomic layer deposition process, though any other suitable deposition process can be used.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.

Abstract: A substrate to be processed in a high temperature processing chamber is preheated to avoid the problems associated with thermal shock when the substrate is dropped onto a heated susceptor. Preheating is effected by holding the substrate over a susceptor maintained at or near the processing temperature until the temperature of the substrate approaches the processing temperature. Thus, wafer warping and breakage are greatly reduced, and wafer throughput is improved because of time saved in maintaining the susceptor at constant temperature without cool down and reheat periods.

Abstract: Wafer buffering systems for use with a wafer processing system include a frame and wheel. The wheel includes a plurality of shelves for supporting a plurality of wafer carriers. The wheel is supported by the frame for rotation about a generally horizontal axis. The plane of the wheel faces a semiconductor processing system (e.g., a cluster tool) with an intervening wafer transfer robot located preferably between the wheel and the semiconductor processing system. A cassette transfer system moves cassettes from the wheel to a port for interfacing with the wafer transfer robot. In another arrangement, a horizontal carousel stocks cassettes above the processing system.

Abstract: Improvements in the design of a low mass wafer holder are disclosed. The improvements include the use of peripherally located, integral lips to space a wafer or other substrate above the base plate of the wafer holder. A uniform gap is thus provided between the wafer and the base plate, such as will temper rapid heat exchanges, allow gas to flow between the wafer and wafer holder during wafer pick-up, and keep the wafer holder thermally coupled with the wafer. At the same time, thermal disturbance from lip contact with the wafer is reduced. Gas flow during pick-up can be provided through radial channels in a wafer holder upper surface, or through backside gas passages. A thicker ring is provided at the wafer holder perimeter, and is provided in some embodiments as an independent piece to accommodate stresses accompanying thermal gradients. Self-centering mechanisms are provided to keep the wafer holder centered relative to a spider which is subject to differential thermal expansion.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: A dual-arm wafer hand-off assembly includes a pair of pickup arms for transferring wafers within a wafer processing system. The two pickup arms are adapted to move such that the wafer on one of the arms can be positioned over the other arm and handed off. In one version, a Bernoulli-style wand translates along a linear guideway and may be positioned over a paddle-style pickup arm. The wafer carried by the Bernoulli wand can be handed off to the paddle by shutting off the flow of gas from the Bernoulli wand jets. The two pickup arms may be mounted on linear slides and adapted to translate between a load/unload chamber and a processing chamber, or the guideway may be adapted to rotate to allow transfer of wafers to multiple processing chambers in a cluster system. One of the pickup arms is preferably an all-quartz Bernoulli-style pickup arm having a proximal arm portion and a distal wand.