Abstract: A dual-arm wafer hand-off assembly includes a pair of pickup arms for transferring wafers within a wafer processing system. The two pickup arms are adapted to move such that the wafer on one of the arms can be positioned over the other arm and handed off. In one version, a Bernoulli-style wand translates along a linear guideway and may be positioned over a paddle-style pickup arm. The wafer carried by the Bernoulli wand can be handed off to the paddle by shutting off the flow of gas from the Bernoulli wand jets. The two pickup arms may be mounted on linear slides and adapted to translate between a load/unload chamber and a processing chamber, or the guideway may be adapted to rotate to allow transfer of wafers to multiple processing chambers in a cluster system. One of the pickup arms is preferably an all-quartz Bernoulli-style pickup arm having a proximal arm portion and a distal wand.

Abstract: Methods are provided for forming uniformly thin layers in magnetic devices. Atomic layer deposition (ALD) can produce layers that are uniformly thick on an atomic scale. Magnetic tunnel junction dielectrics, for example, can be provided with perfect uniformity in thickness of 4 monolayers or less. Furthermore, conductive layers, including magnetic and non-magnetic layers, can be provided by ALD without spiking and other non-uniformity problems. The disclosed methods include forming metal oxide layers by multiple cycles of ALD and subsequently reducing the oxides to metal. The oxides tend to maintain more stable interfaces during formation.

Abstract: Described herein is a process chamber with a substantially all-quartz interior surface. The preferred embodiments have upper and lower walls being curved in both the x-z and y-z planes. In one embodiment, the chamber has thin upper and lower dome walls made from a generally transparent material such as quartz, each with a convex exterior surface and a concave interior surface. These walls are joined at their side edges to a cylindrical side wall, preferably formed from a generally translucent material such as bubble quartz. The upper and lower walls and the side wall substantially enclose an all-quartz interior surface, except for apertures used for gas inlet and outlet, wafer intrusion and extraction and wafer retention. An internal reinforcement extends along the entire interior perimeter of the chamber to provide additional strength and support to the chamber. An external reinforcement surrounds the cylindrical side wall to confine outward expansion of the chamber.

Abstract: Multiple sequential processes are conducted in situ in a single-wafer processing chamber, particularly for forming ultrathin dielectric stacks of high quality. The chamber exhibits single-pass, laminar gas flow, facilitating safe and clean sequential processing. Furthermore, a remote plasma source widens process windows, permitting isothermal sequential processing and thereby reducing the transition time for temperature ramping between in situ steps. In exemplary processes, extremely thin interfacial silicon oxide, nitride and/or oxynitride is grown, followed by in situ silicon nitride deposition. Cleaning, anneal and electrode deposition can also be conducted in situ, reducing transition time without commensurate loss in reaction rates.

Abstract: Improvements in the design of a low mass wafer holder are disclosed. The improvements include the use of peripherally located, integral lips to space a wafer or other substrate above the base plate of the wafer holder. A uniform gap is thus provided between the wafer and the base plate, such as will temper rapid heat exchanges, allow gas to flow between the wafer and wafer holder during wafer pick-up, and keep the wafer holder thermally coupled with the wafer. At the same time, thermal disturbance from lip contact with the wafer is reduced. Gas flow during pick-up can be provided through radial channels in a wafer holder upper surface, or through backside gas passages. A thicker ring is provided at the wafer holder perimeter, and is provided in some embodiments as an independent piece to accommodate stresses accompanying thermal gradients. Self-centering mechanisms are provided to keep the wafer holder centered relative to a spider which is subject to differential thermal expansion.

Abstract: Described herein is a process chamber with a substantially all-quartz interior surface. The preferred embodiments have upper and lower walls being curved in both the x-z and y-z planes. In one embodiment, the chamber has thin upper and lower dome walls made from a generally transparent material such as quartz, each with a convex exterior surface and a concave interior surface. These walls are joined at their side edges to a cylindrical side wall, preferably formed from a generally translucent material such as bubble quartz. The upper and lower walls and the side wall substantially enclose an all-quartz interior surface, except for apertures used for gas inlet and outlet, wafer intrusion and extraction and wafer retention. An internal reinforcement extends along the entire interior perimeter of the chamber to provide additional strength and support to the chamber. An external reinforcement surrounds the cylindrical side wall to confine outward expansion of the chamber.

Abstract: A method and apparatus for transferring a semiconductor wafer in both a theta axis and a z-axis is provided. The apparatus is able to maintain maximum process and wafer throughput while minimizing the footprint of the processing machine by utilizing the concept of “vertical integration” to maximize the use of process slots and minimize the machine foot print. The wafer lift apparatus includes a bipolar electrostatic pick-up for engaging the article at an off-center position near an edge thereof. The electrostatic pick-up is positioned near one end of a transfer arm, the other end of the transfer arm being connected to a drive means for rotating the transfer arm and electrostatic pick-up in the theta axis, or vertically moving the transfer arm and electrostatic pick-up in the z-axis. The electrostatic pick-up is preferably connected to a power source by inductive coupling.

Abstract: Multiple sequential processes are conducted in situ in a single-wafer processing chamber, particularly for forming ultrathin dielectric stacks of high quality. The chamber exhibits single-pass, laminar gas flow, facilitating safe and clean sequential processing. Furthermore, a remote plasma source widens process windows, permitting isothermal sequential processing and thereby reducing the transition time for temperature ramping between in situ steps. In exemplary processes, extremely thin interfacial silicon oxide, nitride and/or oxynitride is grown, followed by in situ silicon nitride deposition. Cleaning, anneal and electrode deposition can also be conducted in situ, reducing transition time without commensurate loss in reaction rates.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.

Abstract: A generally horizontally-oriented quartz CVD chamber is disclosed with front and rear chamber divider plates adjacent a centrally positioned susceptor and surrounding temperature control ring which divide the chamber into upper and lower regions. Improvement to the lifetime of CVD process components and related throughput improvements are disclosed. A getter plate for attracting some of the unused reactant gas is positioned downstream from the susceptor extending generally parallel to and spaced between the divider plate and the upper chamber wall. This getter plate also minimizes deposition on the chamber walls and improves the efficiency of a cleaning step. Reradiating elements are also located adjacent side walls of the chamber to heat cooler chamber wall areas. The getter plate and the reradiating elements plus the susceptor and surrounding ring are all made of solid chemical vapor deposited SiC to improve the life of the chamber.

Abstract: The invention is a carrier comprising three support elements connected by an underlying frame. The periphery of a wafer rests upon the support elements. The invention also comprises a wafer handler with a plurality of arms. Spacers space the carrier above a base plate associated with a station in a wafer handling area. An arm slides beneath the frame and between the spacers, but the handler does not contact the wafer. A method of using the handler and carrier is provided where the handler lifts and rotates the carrier with the wafer through various stations in a wafer handling area. A control device reduces the handler speed only at critical points of the processing cycle. The handler is capable of moving a plurality of carriers and wafers simultaneously.

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.

Abstract: A method is disclosed for forming an ultrathin oxide layer of uniform thickness. The method is particularly advantageous for producing uniformly thin interfacial oxides beneath materials of high dielectric permittivity, or uniformly thin passivation oxides. Hydrofluoric (HF) etching of a silicon surface, for example, is followed by termination of the silicon surface with ligands larger than H or F, particularly hydroxyl, alkoxy or carboxylic tails. The substrate is oxidized with the surface termination in place. The surface termination and relatively low temperatures moderate the rate of oxidation, such that a controllable thickness of oxide is formed. In some embodiments, the ligand termination is replaced with OH prior to further deposition. The deposition preferably includes alternating, self-limiting chemistries in an atomic layer deposition process, though any other suitable deposition process can be used.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design.

Abstract: A system for facilitating wafer transfer comprises a susceptor unit consisting of an inner susceptor section which rests within an outer susceptor section. A vertically movable and rotatable support spider located beneath the susceptor unit can rotate into positions to engage either the inner or the outer susceptor sections. When the inner section is engaged, the support spider lifts the inner section vertically out of the outer section. When the outer section is engaged, the support spider raises and lowers the entire susceptor unit. A robotic arm end effector engaging only the lower surface of the outer edge of the wafer permits hot wafer pick-up and unloading by the inner susceptor section. Several end effectors are disclosed that minimize non-uniform thermal effect on the substrate.

Abstract: A method is disclosed for depositing silicon with high deposition rates and good step coverage. The process is performed at high pressures, including close to atmospheric pressures, at temperatures of greater than about 650° C. Silane and hydrogen are flowed over a substrate in a single-wafer chamber. Advantageously, the process maintains good step coverage and high deposition rates (e.g., greater that 50 nn/min) even when dopant gases are added to the process, resulting in commercially practicable rates of deposition for conductive silicon. Despite the high deposition rates, step coverage is sufficient to deposit polysilicon into extremely deep trenches and vias with aspect ratios as high as 40:1, filling such structures without forming voids or keyholes.

Abstract: A method is provided for treating wafers on a low mass support. The method includes mounting a temperature sensor in proximity to the wafer, which is supported on the low mass support, such that the sensor is only loosely thermally coupled to the wafer. A temperature controller is programmed to critically tune the wafer temperature in a temperature ramp, though the controller directly controls the sensor temperature. A wafer treatment, such as epitaxial silicon deposition, is started before the sensor temperature has stabilized. Accordingly, significant time is saved for the treatment process, and wafer throughput improved.

Abstract: An apparatus and method for clamping and heating a wafer without using moving parts and without exposing the wafer to external stress is provided. A high backside wafer pressure which provides efficient heat transfer from a heated substrate support to the wafer is offset by a high frontside wafer pressure higher than or lower than the backside wafer pressure. The high frontside pressure reduces wafer stress by providing a uniform frontside/backside pressure and presses the wafer against the heated substrate support. A continuous gas purge for providing a viscous flow across the wafer to carry away desorbed contaminants, and frontside heating elements for improving desorption are provided.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.