Abstract: A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.

Abstract: A high-frequency cosmetic treatment apparatus capable of preventing local heating of a skin is provided. The high-frequency cosmetic treatment apparatus includes: a portable casing; side-by-side electrodes disposed at a tip portion of the casing with a predetermined interval provided therebetween, and having treatment surfaces to be contacted with a skin of a user; and a first power supply disposed in the casing, and to supply a high-frequency current to the pair of side-by-side electrodes.

Abstract: There is provided a low-frequency application device capable of applying a low-frequency voltage in synchronization with emitted music and preventing an unexpected large voltage from being suddenly supplied to a human body. A w-frequency application device, comprising: an audio processor to output audio signals; a filter to pass audio signals in a predetermined frequency band among the audio signals; a signal generator to generate a pulse signal by receiving an audio signal at a preset level or higher among the audio signals passed through the filter; electrodes to supply current to a human body; a voltage generator to generate a low-frequency pulse voltage to supply current corresponding to the voltage to the electrodes; and a controller to control output of the voltage by the pulse signal.

Abstract: In the tapping device for producing beautiful skin, a Head contacts with skin. A Tapping mechanism pats the skin facing the Head with a Pad. The Tapping mechanism is equipped with the Pad at one end, and has a Shaft from which the Head projects and rolls back by piston actions. A Biasing member biases the Shaft toward one side of the piston actions. A Wire rod empowers the Shaft towards the direction resisting the biasing power of the Biasing member when tension is provided. An Actuator provides tension intermittently in a Wire rod, the tension of the wire rod and biasing of the bias member providing piston actions.

Abstract: A warm-cool beauty treatment device, comprising: a Peltier element of a plate shape having a first surface configured to generate heat, and a second surface configured to absorb heat; a heat sink including—a first section touching the first surface, and a second section connecting the first section thermally; a first plate connected to the first surface thermally via the heat sink; a second plate connected to the second surface thermally; a blower configured to produce air flow to release the heat of the second section; and a power supply configured to supply electric power to the Peltier element and the blower.

Abstract: A cache unit comprising a register file that selects an entry indicated by a cache index of n bits (n is a natural number) that is used to search for an instruction cache tag, using multiplexer groups having n stages respectively corresponding to the n bits of the cache index. Among the multiplexer groups having n stages, a multiplexer group in an mth stage has 2(m-1) multiplex circuits. The multiplexer group in the mth stage uses a value of an mth bit (m is a natural number equal to or less than n) from the least significant bit in the cache index as a control signal. The multiplexer group in the mth stage switches all multiplex circuits included in the multiplexer group in the mth stage in accordance with the control signal.

Abstract: A processor holds, in a plurality of respective cache lines, part of data held in a main memory unit. The processor also holds, in the plurality of respective cache lines, a tag address used to search for the data held in the cache lines and a flag indicating the validity of the data held in the cache lines. The processor executes a cache line fill instruction on a cache line corresponding to a specified address. Upon execution of the cache line fill instruction, the processor registers predetermined data in the cache line of the cache memory unit which has a tag address corresponding to the specified address and validates a flag in the cache line having the tag address corresponding to the specified address.

Abstract: A laser depilatory device is provided where the tips of skin hairs can be trimmed evenly after cauterization and the skin hair can he removed efficiently with lower power consumption, while preventing the direct adverse influent of het on the human skim The laser device includes: a housing including a contacting surface to which a skin surface is contacted and a recessed portion formed on the contacting surface; a laser light generating section disposed in the housing for generating laser light; and a first hole portion formed on an inner wall surface of the recessed portion for emitting the laser light through a space inside the recessed portion towards the inner wall.

Abstract: A processing apparatus, which contains a processor that executes a program includes a series of instructions, includes a log recording unit configured to record an operation log of the processing apparatus; a managing unit configured to control a recording operation performed by the log recording unit and read the operation log recorded in the log recording unit; an input unit configured to detect, from among the series of instructions of the executed program; a start instruction that starts a process for delivering a control instruction destined for the managing unit to the managing unit and deliver the control instruction to the managing unit in response to the start instruction; and an output unit configured to receive the operation log read by the managing unit.

Abstract: According to an aspect of an embodiment of the invention, an arithmetic processing unit includes a first cache memory unit that holds a part of data stored in a storage device; an address register that holds an address; a flag register that stores flag information; and a decoder that decodes a prefetch instruction for acquiring data stored at the address in the storage device. The arithmetic processing unit further includes an instruction execution unit that executes a cache hit check instruction instead of the prefetch instruction on the basis of a decoded result when the flag information is held, the cache hit check instruction allowing for searching the first cache memory unit with the address to thereby make a first cache hit determination that the first cache memory unit holds the data stored at the address in the storage device.

Abstract: A processor including a circuit unit includes a state information holding unit, a direction controller, a direction generator, and a direction execution unit. The state information holding unit holds state information indicating a state of the circuit unit. The direction controller decodes a first direction for generating a control direction that is contained in a program. The direction generator generates a second direction when the first direction decoded by the direction controller is a direction for generating the second direction for reading the state information from the state information holding unit. The direction execution unit reads the state information from the state information holding unit based on the second direction generated by the direction generator so as to store the state information in a register unit that is capable of being read from a program.

Abstract: A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.

Abstract: A cache memory controlling unit includes a plurality of STBs for maintaining 8-byte store data received from an execution unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM. The cache memory controlling unit having such a structure obtains data-not-to-be-stored from the DATA-RAM, stores the obtained data in the FCDR, and merges the stored data with data-to-be-stored in the store data output from the execution unit and stored in the STBs or the WBs to generate new store data. The cache memory controlling unit then writes the generated new store data in the DATA-RAM, generates an ECC from the new store data, and writes the ECC in the ECC-RAM.

Abstract: An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices.

Abstract: A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.

Abstract: Disclosed is a high-frequency treatment device provided with: an oscillator circuit and an amplification circuit that generate a high-frequency signal; and a head that holds terminals (41x and 41y) that run the high-frequency signal generated by the oscillator circuit and the amplification circuit through skin. To address the problem that running an excessively strong high-frequency signal through skin carries the danger of causing burns or other accidents, the disclosed high-frequency treatment device is provided with a current-carrying region change means that changes the region of the skin to which current is applied, from one of the terminals to the other, while the high-frequency signal is being applied.

Abstract: Disclosed herein is a micro TLB which includes a CAM section having a plurality of CAM circuits, each stores address information which represents correlation between a virtual address and a physical address; and a write control section which directs writing of the address information into each CAM circuit pointed by a write pointer, when a new address information is requested to be stored, wherein the micro TLB being configured to increment the write pointer, if the address information stored in each CAM circuit pointed by the write pointer has been used for address translation, so as to hold a recently-used address information while preventing the CAM circuit, having indication of use of the address information, from being overwritten with the new address information.

Abstract: [Problem to be Solved] It cannot be said that the irradiation range of laser light is sufficiently wide, a lot of labor is taken to irradiate the skin with laser light, and there has been a problem that efficiency of cosmetic treatment is bad. [Solution] A laser treatment device is provided with a laser light source 40 consisting of at least one or more VCSEL array 41 that has two or more VCSEL elements 41s arranged on a single wafer and emits laser light for irradiating the skin. The laser treatment device may also be provided with: a reflected-light power detection means that detects power of reflected light of the light irradiating an irradiation part, the reflected light reflected from the irradiation part; and a control means that adjusts, in accordance with the power of the reflected light detected by the reflected-light power detection means, power of the laser light emitted from the light source means.

Abstract: In the tapping device for producing beautiful skin, a Head contacts with skin. A Tapping mechanism pats the skin facing the Head with a Pad. The Tapping mechanism is equipped with the Pad at one end, and has a Shaft from which the Head projects and rolls back by piston actions. A Biasing member biases the Shaft toward one side of the piston actions. A Wire rod empowers the Shaft towards the direction resisting the biasing power of the Biasing member when tension is provided. An Actuator provides tension intermittently in a Wire rod, the tension of the wire rod and biasing of the bias member providing piston actions.

Abstract: A pre-fetch control apparatus is equipped with a next-line pre-fetch control apparatus 38. An address overflowed from a pre-fetch address queue 26 is stored in the next-line pre-fetch control apparatus 38. An access address issued by a processor unit and stored in a register 25 is compared with the address stored in the next-line pre-fetch control apparatus 38 and, if the two addresses are identical, a value obtained by adding a data block size ? of cache memory to the address stored in the next-line pre-fetch control apparatus 38 is stored again in the next line pre-fetch control apparatus 38. When the address issued by the processor unit is identical with that stored in the next-line pre-fetch control apparatus 38 a predetermined number of times, the occurrence of continuous accesses is presumed and pre-fetching is carried out for all addresses that have not hit the pre-fetch address queue.