Patents by Inventor Iwao Yamazaki

Iwao Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060026365
    Abstract: In an information processing apparatus (10) that includes a cache memory (560) formed from at least one hierarchy, and a pre-fetch command that speculatively transfers data or a command from a main storage (30) to the cache memory, a cache controller (510) provides control to execute the pre-fetch command such that a virtual address is converted to a physical address using a conversion table, and the virtual address and the physical address are stored as a pair if the conversion succeeds.
    Type: Application
    Filed: November 12, 2004
    Publication date: February 2, 2006
    Applicant: Fujitsu Limited
    Inventor: Iwao Yamazaki
  • Publication number: 20060026399
    Abstract: In order to increase the operation efficiency of the operation register for holding store data when executing store instruction to store data in a predetermined store area on the main memory or the cache memory, in the present invention, an instruction processing section is adapted so as, when an operation register holding the operation result is determined, causes the operation result to be issued from the operation register to store buffers as store data; when the store data are held by the store buffers before the store instruction is held by store ports, a restraint section restrains a reset section from setting a store data hold flag to OFF at a point of time when the store instruction is held by the store ports to maintain the store data hold flag to ON.
    Type: Application
    Filed: November 9, 2004
    Publication date: February 2, 2006
    Applicant: Fujitsu Limited
    Inventors: Takashi Miura, Iwao Yamazaki
  • Publication number: 20060026369
    Abstract: A store data control device that controls a store buffer and a write buffer that temporarily retains store data, and that executes a merging process on store data when transferring store data from the store buffer to the write buffer. The store data control device acquires a buffer state of at least one of the store buffer and the write buffer, and based on the buffer state acquired controls whether to start or cancel a queuing process corresponding to the merging process.
    Type: Application
    Filed: November 19, 2004
    Publication date: February 2, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Iwao Yamazaki
  • Publication number: 20060026363
    Abstract: A central processor executes at least a load command, a store command, and a prefetch command based on an out-of-order processing for processing commands by changing the order of executing the commands. A valid MIB detector detects the number of primary cache MIBs that hold requests of a primary cache for reference to data stored in the main storage. An MIB controller controls to hold in the primary cache MIBs the reference requests according to the load command or the store command in preference to the reference requests according to the prefetch command, when the detected number of the cache buffers reaches a predetermined number.
    Type: Application
    Filed: November 24, 2004
    Publication date: February 2, 2006
    Applicant: Fujitsu Limited
    Inventor: Iwao Yamazaki
  • Publication number: 20060026380
    Abstract: A method for controlling an address conversion buffer, constituted on a processor capable of executing a plurality of threads simultaneously on one core, includes registering address conversion information in an entry of the address conversion buffer that includes a first memory area usable by one of the threads and a second memory area shared among all the threads, allocating a part of the second memory area as a swap area of the first memory area, and transferring data in the swap area to the first memory area, based on thread switching executed by the processor.
    Type: Application
    Filed: November 12, 2004
    Publication date: February 2, 2006
    Applicant: Fujitsu Limited
    Inventors: Masanori Doi, Iwao Yamazaki
  • Publication number: 20060026381
    Abstract: Context information pertaining to the virtual address is obtained, and a storage location for storing the address translation information is determined based on the context information.
    Type: Application
    Filed: November 12, 2004
    Publication date: February 2, 2006
    Applicant: Fujitsu Limited
    Inventors: Masanori Doi, Iwao Yamazaki, Tsuyoshi Motokurumada, Masahiro Doteguchi
  • Publication number: 20060026362
    Abstract: A central processor requests for reference to data stored in a main storage for each of a plurality of threads. A thread identification information obtaining unit obtains thread identification information that identifies the threads. A valid MIB detector detects the number of the primary cache MIBs that hold requests of the cache for reference to data stored in the mains storage, for each thread based on the thread identification information. The MIB controller controls to hold reference requests in the primary cache MIBs such that the number of the primary cache MIBs detected for each thread does not exceed a predetermined number.
    Type: Application
    Filed: November 19, 2004
    Publication date: February 2, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Iwao Yamazaki
  • Publication number: 20060026382
    Abstract: The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer for storing address translation pairs and thread information, a retriever for retrieving an address translation pair of a virtual addresses identical to said virtual address from the address translation buffer for translating the virtual address into a physical address, a determination unit for determining, when plural addresses translation pairs are retrieved by the retriever, whether or not two or more of said thread information are identical among plural thread information corresponding to plural address translation pairs, and a multi-hit controller for suppressing output of multi-hits and directing execution of address translation if the thread information are determined to be different according to the determination unit.
    Type: Application
    Filed: November 15, 2004
    Publication date: February 2, 2006
    Applicant: Fujitsu Limited
    Inventors: Takahito Hirano, Iwao Yamazaki, Tsuyoshi Motokurumada
  • Patent number: 6981121
    Abstract: An arithmetic unit performs an arithmetic operation, and outputs data obtained as a result of the arithmetic operation. The data output from the arithmetic unit is stored in a store buffer. The data read from the store buffer is stored in cache memory. A first alignment circuit allows an alignment circuit to realign the data output from the arithmetic unit and stored in the store buffer, and the second alignment circuit realigns data read from the store buffer and stored in the cache memory.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: December 27, 2005
    Assignee: Fujitsu Limited
    Inventors: Takashi Miura, Iwao Yamazaki
  • Patent number: 6973345
    Abstract: Disclosed is an exercise amount measuring device comprising: means for calculating the body fat percentage from the bioelectrical impedance of an individual and the personal data of the individual; means for determining the body shape of the individual and the amount of the basal metabolism of the individual from the personal data and the calculated body fat percentage; means for calculating the “to-be-consumed” body fat amount by subtracting a given body fat percentage set for a goal from the measured body fat percentage; means for calculating the “to-be-consumed” calorie amount required for reducing the “to-be-consumed” body fat amount; means for changing the “to-be-consumed” calorie amount to the corresponding amount of exercise and for setting the so converted amount of exercise as a goal; means for calculating the actual amount of exercise and the consumed calorie amount from the detected motions of the living body and the acceleration of the motion of the living body; and means for calculating the remai
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: December 6, 2005
    Assignee: YA-MAN Ltd.
    Inventors: Iwao Yamazaki, Kimiyo Yamazaki
  • Publication number: 20050210204
    Abstract: A central processing device includes a plurality of sets of instruction processors that concurrently execute a plurality of threads and primary data cache devices. A secondary cache device is shared by the primary data cache device belonging to different sets. The central processing device also includes a primary data cache unit and a secondary cache unit. The primary data cache unit makes an MI request to the secondary cache unit when a cache line with a matching physical address but a different thread identifier is registered in a cache memory, performs an MO/BI based on the request from the secondary cache unit, and sets a RIM flag of a fetch port. The secondary cache unit makes a request to the primary cache unit to perform the MO/BI when the cache line for which MI request is received is stored in the primary data cache unit by a different thread.
    Type: Application
    Filed: May 6, 2005
    Publication date: September 22, 2005
    Applicant: FUJITSU LIMITED
    Inventor: Iwao Yamazaki
  • Publication number: 20050177139
    Abstract: A laser depilator comprising a unit for removing hairs from the skin, a light source for irradiating laser light, and a lens for irradiating the skin with the laser light irradiated from the light source while deforming the beam shape so as to conform to the shape of a region of the skin from which hairs are removed by the hair removing unit. Since removal of hairs shielding the laser light and irradiation of laser light for damaging hair roots can be carried out continuously, efficiency of depilation treatment can be enhanced. Furthermore, depilation can be carried out effectively through a simple arrangement because a shaved skin surface can be irradiated with laser light over a relatively wide range using a lens.
    Type: Application
    Filed: August 15, 2002
    Publication date: August 11, 2005
    Inventors: Iwao Yamazaki, Akitsugu Yamazaki
  • Publication number: 20050177060
    Abstract: A display of the quantities of bone, water and/or muscle and a pulse health instrument in which the weight of bone or the weight rate of bone, the quantity of water and/or the quantity of muscle are measured and displayed to serve for sound diet and health management. Body fat rate is calculated by measuring the body impedance, quantity of bone, weight of bone, weight rate of bone, quantity of water and/or quantity of muscle are calculated based on the body fat rate and personal information inputted from a user, e.g. sex, age, height, body weight, length around wrist, length around ankle, and the like, and the results are displayed at a display section 105. Furthermore, the type of quantity of bone based on the correlation between the weight rate of bone and the body weight is judged and displayed in the matrix display region 111 of the display section 105.
    Type: Application
    Filed: June 9, 2003
    Publication date: August 11, 2005
    Inventors: Iwao Yamazaki, Akitsugu Yamazaki
  • Patent number: 6915406
    Abstract: A first table stores operand data for translation of operand virtual address into a physical address. A second table stores instruction data for translation of instruction virtual address into a physical address. The first and the second tables are formed in one memory. If operand access and instruction access are generated simultaneously, the operand access is executed with priority and the instruction virtual address is held in a wait register after that the instruction access is executed after finishing the operand access based on a wait instruction virtual address.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: July 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Takuma Chiba, Tsuyoshi Motokurumada, Iwao Yamazaki
  • Patent number: 6904614
    Abstract: A glove with electrodes comprises a pair of flat electrodes 3, 4 which are disposed with a space therebetween on the surface of the palm side of a glove body 2 which is made of an electrical insulating material, an operation panel 30 which is fitted in the vicinity of the wrist on the back or the palm of the glove body 2 to control to supply electricity to the flat electrodes 3, 4, and lead wires 5, 6 which are fitted to the glove body 2 and electrically connect output terminals 40 of the operation panel 30 and the respective flat electrodes 3, 4. The respective flat electrodes 3, 4 are touched with a little space between them to a portion of the human body, and a current is passed to the portion for treatment. Thus, the glove body 2 can be put on one hand only to easily treat from a wide area to a small portion by passing a current to any portion of the human body.
    Type: Grant
    Filed: November 11, 2002
    Date of Patent: June 14, 2005
    Assignee: Ya-Man Ltd.
    Inventors: Iwao Yamazaki, Akitsugu Yamazaki
  • Publication number: 20050101994
    Abstract: A beauty culture device capable of effecting facial shape-up in a comfortable and easy manner. Received in a mask (1) to be put on a face with the eye and nose portions cut off is a V-shaped airbag (2) closely contacted with the right and left cheeks with the jaw disposed therebetween, and a pair of right and left planar electrodes (3) to be contacted with the right and left cheeks and the jaw for electric conduction are stuck to the surface on the side opposed to the face. Further, a belt-like restraint (12) for fixing the mask (1) on the face by using a surface fastener for tightening is attached to the back of the mask (1).
    Type: Application
    Filed: August 8, 2001
    Publication date: May 12, 2005
    Inventors: Iwao Yamazaki, Yoshihiro Izawa
  • Patent number: 6883077
    Abstract: In an information processsing unit with key controlled protection, since it takes a long time to fetch a storage key from key storage, an instruction and computation unit of a CPU receives data from a memory control unit of the CPU before a key is received, and then the transferred storage key is checked.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: April 19, 2005
    Assignee: Fujitsu Limited
    Inventors: Hiroaki Kimura, Yuji Shirahige, Iwao Yamazaki
  • Publication number: 20050054957
    Abstract: A supersonic beauty treatment device capable of effecting a beauty treatment for the skin and of slimming a selected portion of the body. A face beauty treatment head and body beauty treatment head are prepared, and either one is selectivley attached to the casing of the device. The casing has a tepped receptacle made on its front. Each head has a plug projecting from its base. The plug has threads fromed on its outer circumference. Thus, the head can be attached to the casing by screwing the plug in the receptacle, and two sets of switch contacts are formed on both sides of the center of the insulating bottoem of the receptacle. The electrically conductive inner circumference wall of the receptacle is grounded. The plug as a contact formed at is center, corresponding to the center contact of the receptacle.
    Type: Application
    Filed: September 21, 2001
    Publication date: March 10, 2005
    Inventors: Iwao Yamazaki, Yoshihiro Izawa
  • Patent number: 6860835
    Abstract: Disclosed is an exercise amount measuring device using as an exercise signal generator an inclination detector commercially available, which can detect two-dimensional movements. Use of such inclination detectors facilitates the assembly of exercise amount measuring devices. The inclination detector 1 is connected to a counter circuit via an input circuit, and the input circuit and the counter circuit are connected to an MPU via an input-and-output port. The input circuit comprises a CR circuit or a flip-flop circuit. The counter circuit counts input pulses post-chattering exclusion, which input pulses are caused by the on-and-off switching actions, which are brought every time the contact ball touches selected contact electrodes in the inclination detector.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: March 1, 2005
    Assignee: Ya-Man Ltd.
    Inventors: Iwao Yamazaki, Yoshihiro Izawa, Kimiyo Yamazaki
  • Patent number: D504516
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: April 26, 2005
    Assignee: Ya-Man Ltd.
    Inventor: Iwao Yamazaki