Patents by Inventor János Farkas

János Farkas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7691756
    Abstract: A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: April 6, 2010
    Assignee: NXP B.V.
    Inventors: Janos Farkas, Srdjan Kordic, Cindy Goldberg
  • Patent number: 7674725
    Abstract: A treatment solution for a semiconductor wafer comprising water, a passivating reagent and a surfactant. The treatment solution is either mixed with a cleaning fluid, a rinsing fluid or a drying vapor, and is used in a cleaning apparatus employing a Marangoni dryer.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: March 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Janos Farkas, Sebastien Petitdidier
  • Publication number: 20100054157
    Abstract: There is disclosed a manner of managing the active topology, that is the scheme for forwarding data, in a computer network such as an Ethernet local area network. A root bridge is selected from a plurality of bridges in the network; the root bridge calculating at least one spanning tree from a topology database that has been populated by bridge neighbor information gleaned from link state advertising messages. The root bridge may also calculate an alternate topology for implementation in the event a failure condition that affects the primary spanning tree is detected. The root bridge then advertises the spanning tree and remotely configures the port states of the bridges in the spanning tree through tree advertising messages that the bridges are arranged to process and set their ports accordingly.
    Type: Application
    Filed: January 18, 2008
    Publication date: March 4, 2010
    Inventors: János Farkas, Csaba Antal, Attila Takács, Panagiotis Saltsidis
  • Patent number: 7660242
    Abstract: A call admission control system and method for Internet Protocol (IP) Differentiated Services (DiffServ) network having at least one node for interpreting signaling messages and controlling traffic load in the network. The method consists of an initialization (601) and a real-time phase (602). In initialization phase (601), coefficients of the approximating hyperplanes are computed (61) and stored (62). This phase is repeated when the descriptor of a traffic class changes (63), which usually happens when nodes are configured or reconfigured. A traffic mix is admissible (67), if for each real-time traffic class both the stability (65) and the delay (66) constraints are fulfilled. Stability is tested by evaluating the number of lost packets and comparing it to the tolerated packet loss ratio for each class in that queue. Delay constraint is tested by checking if the traffic mix is below at least one of the approximating hyperplanes in the space of number of sessions for each class.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: February 9, 2010
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventors: Gergely Matefi, Csaba Antal, Janos Farkas
  • Publication number: 20100020722
    Abstract: A network (NW1) has switches (S1-S7), routers (R1-R4) and a management node (NMS1) interconnected by links (PL1) in a spanning tree (ST1) and links (PL2) to blocked interfaces. Switches and routers have the IP address of the management node. The nodes are discovered by the management node (NMS1) broadcasting a ping message (PiI) and on reply (RPiI) adds the nodes to the topology. The spanning tree (ST1) is discovered in that the management node retrieves address forwarding tables from the switches and assigns them a ranking value. From the highest ranked node successively lower ranked nodes are connected. The blocked interfaces (PL2) are discovered by configuring a VLAN (VLANI) to include only the spanning tree (ST1) and disabling the latter The blocked interfaces are turned off and on, matching link down traps are noted and the corresponding link (PL2) is discovered. The status of the interfaces (1, 2, 3 . . . ) are cyclically checked for changes and new links and network segments are added.
    Type: Application
    Filed: October 9, 2007
    Publication date: January 28, 2010
    Inventors: János Farkas, Vinicius Garcia de Oliveira, Marcos Rogério Salvador
  • Publication number: 20090301867
    Abstract: A system for processing a semiconductor substrate during fabrication of semiconductor devices provides a plurality of semiconductor substrate processing stations in a physically integrated system, as well as a semiconductor substrate transport system for transporting a semiconductor substrate between the respective processing stations. In particular, the processing system according to the present invention favors the use of liquid phase process steps, particularly deposition process steps, instead of gas or vapor phase processing. Even more particularly, the system contemplates deposition of a metallic barrier layer 30 on the semiconductor substrate in liquid phase.
    Type: Application
    Filed: February 24, 2006
    Publication date: December 10, 2009
    Applicant: CITIBANK N.A.
    Inventors: Janos Farkas, Cindy Goldberg, Katie Yu, Srdjan Kordic
  • Publication number: 20090115031
    Abstract: A material for passivating a dielectric layer in a semiconductor device has a molecular structure permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. The contemplated material may be constituted by multiple organic components. A semiconductor device including a layer of the passivating coupling material, and a method of manufacturing such a semiconductor device are also contemplated.
    Type: Application
    Filed: February 24, 2006
    Publication date: May 7, 2009
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Janos Farkas, Maria Luisa Calvo-Munoz, Srdjan Kordic
  • Publication number: 20090094098
    Abstract: Disclosed herein is a method and system for promoting a first wine industry of a first geographical location utilizing a plurality of advertising media. In a first embodiment, the plurality of advertising mediums is selected for promoting the first wine industry. The disclosed method links information of contribution of the first wine industry to a second wine industry. The information is publicized in a plurality of locations. In a second embodiment, the first wine industry is promoted utilizing a web portal. The web portal comprises a first set of information of the first wine industry and a second set of information of the second wine industry. The web portal establishes a virtual link between the first set of information and the second set of information. Further, revenue may be generated through the advertising mediums and targeted advertising.
    Type: Application
    Filed: October 4, 2007
    Publication date: April 9, 2009
    Inventor: Janos Farkas
  • Publication number: 20090045164
    Abstract: During processing of a semiconductor wafer bearing a structure including a low-k dielectric layer, a cap layer and the metal-diffusion barrier layer, a chemical mechanical polishing method applied to remove the metal-diffusion barrier material involves two phases. In the second phase of the barrier-CMP method, when the polishing interface is close to the low-k dielectric material, the polishing conditions are changed so as to be highly selective, producing a negligible removal rate of the low-k dielectric material. The polishing conditions can be changed in a number of ways including: changing parameters of the composition of the barrier slurry composition, and mixing an additive into the barrier slurry.
    Type: Application
    Filed: February 3, 2006
    Publication date: February 19, 2009
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Janos Farkas, Philippe Monnoyer, Brad Smith, Mark Zaleski
  • Publication number: 20080316917
    Abstract: A method of generating spanning trees in a network in which a plurality of network nodes are interconnected by links. The spanning trees are utilized for handling link and node failures. For link failures, each link has at least one tree that does not include that link. For node failures, each node has at least one tree to which the node is connected by a single link. A first spanning tree connects all of the nodes, and from each node one link is left unconnected. A second spanning tree includes all of the nodes and all of the unconnected links. Thus, none of the links is included in both trees. If a node failure prevents other nodes from communicating, a third spanning tree is needed. The method minimizes the number of required trees in large networks of any topology and can be implemented off-line.
    Type: Application
    Filed: October 11, 2005
    Publication date: December 25, 2008
    Inventors: Janos Farkas, Toth Gabor
  • Publication number: 20080291822
    Abstract: The invention relates to failure handling in a tree sructure network (NW1) that has edge nodes (EN1 . . . EN4) and switching nodes (SW1 . . . SW4) interconnected by lines (L1). VLANs (VLAN1-VLAN3) are established such that at least one thereof provides connectivity in case of any single failure in the network. The VLANs can be established by using spanning trees (ST1,ST2,ST3). Among the edge nodes, emitters (EN3) broadcast alive messages (A1,A2,A3) regularly on the VLANs and notifiers (EN2) note the alive messages. A missing alive message indicates a failure (CD1) on one VLAN (VLAN2) and the notifier (EN2) broadcasts corresponding failure messages (F1,F2,F3) on the VLANs. When all the alive messages (A1,A2,A3) appear again the notifier (EN2) broadcasts corresponding repair messages (R1,R2,R3). If the notifiers don't note a failure the nodes (EN1,EN4) with no special role performs a similar function as the notifier (EN2) somewhat slower.
    Type: Application
    Filed: June 14, 2005
    Publication date: November 27, 2008
    Inventors: Janos Farkas, Csaba Antal, Lars Westberg
  • Patent number: 7456105
    Abstract: This disclosure describes a low particle concentration formulation for slurry which is particularly useful in continuous CMP polishing of copper layers during semiconductor wafer manufacture. The slurry is characterized by particle concentrations generally less than 2 wt %, and advantageously less than 1 wt %. In particular embodiments, where the particle concentration is in a range of 50 to 450 PPM, an 8-fold increase in polishing rate over reactive liquid slurries has been realized. Slurries thus formulated also achieve a reduction in defectivity and in the variations in planarity from wafer to wafer during manufacture, by improving the stability of polishing quality. The slurry formulations permit substantial cost savings over traditional 2-component, reactive liquid and fixed/bonded abrasive slurries. In addition the formulations provides an advantageous way during CMP to easily change the selectivity or rate of removal of one film material vs. another.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 25, 2008
    Assignees: AMD, Inc., Motorola, Inc.
    Inventors: Kevin Elliot Cooper, Jennifer Lynn Cooper, Janos Farkas, John C. Flake, Johannes Friedrich Groschopf, Yuri Solomentsev
  • Publication number: 20080287041
    Abstract: A system for removing particles from a polishing pad to improve the efficiency of the removal of material by the polishing pad as part of a chemical-mechanical polishing process, the system comprising a polishing pad; a fluid dispenser arranged to dispense a fluid on the polishing pad; and removal means, wherein the removal means include a heater for increasing the temperature of the fluid dispensed on the polishing pad, and/or voltage means for coupling the polishing pad to a voltage source for repelling charged particles from the polishing pad surface while the fluid dispenser is dispensing the fluid on the polishing pad.
    Type: Application
    Filed: November 8, 2005
    Publication date: November 20, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Srdjan Kordic, Sebastien Petitdidier, Janos Farkas, Silvio Del Monaco
  • Publication number: 20080282778
    Abstract: A method for forming a semiconductor device, the method includes providing a semiconductor substrate, applying a slurry to the semiconductor substrate, wherein the slurry was tested using a testing method includes taking a first undiluted sample from a top of the slurry; determining a first particle size distribution characteristic of the first undiluted sample; taking a second undiluted sample from a bottom of the slurry; determining a second particle size distribution characteristic of the second undiluted sample; and comparing a difference between the first particle size distribution characteristic and the second particle size distribution characteristics with a first predetermined value.
    Type: Application
    Filed: October 25, 2005
    Publication date: November 20, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Philippe Monnoyer, Janos Farkas, Farid Sebaai
  • Publication number: 20080271274
    Abstract: Silicon wafers and the like are cleaned using new scrubber-type apparatus in which measures are taken to compensate for differential cleaning of the central region of the wafer by: using rotary brushes having one or more non-contact portions arranged in the section thereof that faces the central region of the substrate, or toggling the relative position of the wafer and the rotary brushes, or directing cleaning fluid(s) preferentially towards the central region of the wafer. Another aspect of the invention provides scrubber-type cleaning apparatus in which the rotary brushes are replaced by rollers (110). A web of cleaning material (116) is interposed between each roller and the substrate. Various different webs of cleaning material may be used, e.g. a length of tissue, a continuous loop of cleaning material whose surface is reconditioned on each cleaning pass, adhesive material provided on a carrier tape, etc.
    Type: Application
    Filed: April 20, 2005
    Publication date: November 6, 2008
    Applicant: NXP B.V.
    Inventors: Srdjan Kordic, Kevin E. Cooper, Sebastien Petitdidier, Janos Farkas, Jan Van-Hassel
  • Publication number: 20080242110
    Abstract: A process for the formation of a capping layer on a conducting interconnect for a semiconductor device is provided, the process comprising the steps of: (a) providing one or more conductors in a dielectric layer, and (b) depositing a capping layer on an upper surface of at least some of the one or more conductors, characterised in that the process further includes: (c) the step of, prior to depositing the capping layer, reacting the dielectric layer with an organic compound in a liquid phase, the said organic compound having the following general formula: (I) where X is a functional group, R is an organic group or a organosiloxane group, Y1 is either a functional group or an organic group or organosiloxane group, and Y2 is either a functional group or an organic group or organosiloxane group, and where the functional group(s) is/are independently selected from the following: NH2, a secondary amine, a tertiary amine, acetamide, trifluoroacetamide, imidazole, urea, OH, an alkyoxy, acryloxy, acetate, SH, an alky
    Type: Application
    Filed: September 1, 2005
    Publication date: October 2, 2008
    Applicant: NXP B.V.
    Inventors: Janos Farkas, Lynne Michaelson, Srdjan Kordic
  • Publication number: 20080221004
    Abstract: A cleaning solution for a semiconductor wafer comprises ammonia, hydrogen peroxide, a complexing agent and a block copolymer surfactant diluted in water. The cleaning solution can be used in single wafer cleaning tools to remove both particulate contaminants and metallic residues.
    Type: Application
    Filed: May 25, 2005
    Publication date: September 11, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Janos Farkas
  • Publication number: 20080207005
    Abstract: When a semiconductor wafer bears porous dielectric materials it is still possible to perform post-via-etch cleaning of the wafer using aqueous cleaning fluids if, before and/or simultaneously with application of the aqueous cleaning fluid(s), a water-soluble organosilane or like passivation material is used to form a passivation layer on the porous dielectric material.
    Type: Application
    Filed: February 2, 2005
    Publication date: August 28, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Janos Farkas
  • Publication number: 20080197487
    Abstract: A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device.
    Type: Application
    Filed: September 1, 2006
    Publication date: August 21, 2008
    Applicant: NXP B.V.
    Inventors: Janos Farkas, Srdjan Kordic, Cindy Golberg
  • Publication number: 20080194116
    Abstract: A treatment solution for a semiconductor wafer comprising water, a passivating reagent and a surfactant. The treatment solution is either mixed with a cleaning fluid, a rinsing fluid or a drying vapour, and is used in a cleaning apparatus employing a Marangoni dryer.
    Type: Application
    Filed: May 25, 2005
    Publication date: August 14, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Janos Farkas, Sebastien Petitdidier