Abstract: An error correction and/or error detection method reads of stored information data from a storage device; wherein in addition to the information data, code data is read from the storage device. Syndrome data is formed from the information data and the code data in order to determine errors and/or error positions in the read data. For detection of multiple errors, it is verified whether in the case of a determined error position, the information data or code data associated with the relevant storage positions are either all equal to 0, or are all equal to 1.

Abstract: A radiotherapy installation is described, with a treatment head which is arranged on a treatment head support and which has an exit port for a beam generated in a beam generator, and with a patient table. The treatment head support is guided on a first rectilinear guide, which is guided on a second rectilinear guide arranged perpendicular to the first rectilinear guide, in order to move the treatment head relative to the patient table during the radiotherapy.

Abstract: A triggering device for a safety device in an automotive vehicle, in particular for an airbag, has an electrical component that has at least one force sensor and that is attached to the body of the automotive vehicle in such a way that a measurement signal that is dependent on the deformation of the body can be applied at a measurement signal output of the force sensor. An evaluation device for processing the measurement signal is connected to the measurement signal output. The force sensor has at least one piezo element, which is integrated into a CMOS chip together with the evaluation device.

Abstract: There is provided a mobile telephony device, comprising a mobile station that can be connected to a mobile telephony network by using a SIM card. A multiplexer can be connected to the mobile station, the multiplexer holding several SIM cards. An exemplary multiplexer may comprise a first switching component that is configured such that each one of the SIM cards can be connected to the mobile station. The exemplary multiplexer may comprise a second switching component that is configured to switch off the mobile station while one SIM card is being disconnected from the mobile station and another SIM card is being connected to the mobile station.

Abstract: A measuring device for analyzing a lubricant of a bearing. The measuring device has an electromagnetic radiation emitter, a receiving element and a test area that is arranged between the emitter and the receiving element. The measuring device allows for current information on the condition of the lubricant in the bearing to be obtained. At least some sections of the test area are inside the bearing and the receiving element supplies a spectrum of electromagnetic radiation captured by the test area. Also, a bearing and a seal for the bearing and a method for detecting and monitoring the condition of the lubricant of a bearing.

Abstract: The invention relates to a circuit configuration with a serial test interface (TIF) to control a test operation mode, a freely programmable digital processor (CPU), a housing (G) for the accommodation of a test interface (TIF) and the processor (CPU) with terminals or connectors (C0, C1) for data and/or signal exchange with external components and setups. At one of the terminals (C1), a modulated supply voltage (VDD) can be received the transfer of data (d) and or a clock (T) by using at least two voltage levels (V2, V3) that can be controlled and which are different from a supply voltage level (V1) that is designed to feed the circuitry with a supply operating voltage. Furthermore, the invention relates to a serial test operation method for such a circuit configuration.

Abstract: The invention relates to a method and a corresponding device for controlling a memory access, wherein a number of waiting states is established for the memory access to a storage device (FLASH/ROM, RAM, IO module) for a central control unit (CPU). A memory access is made possible in that the number of waiting states for the memory access is established individually as a function of an analysis of an instantaneous state (status) of the central control unit (CPU) and/or a type and/or address of the storage device (FLASH/ROM, RAM, IO module) being accessed.

Abstract: The invention relates to an integrated circuit arrangement with connection contacts for the serial exchange of data and/or signals with external components and apparatuses and with a control apparatus and/or a serial interface for the clocked receiving of data by means of a signal voltage on such a connection contact, which voltage is modulated between at least one low, one middle and one high voltage state. The control apparatus and/or the interface are designed in such a manner that data is sent in a sending mode via the connection contact in that the switching apparatus, after having received a slope changing in particular from the middle voltage state into in particular the higher or the lower voltage state, pulls the voltage state into the in particular opposite lower or higher voltage state. Furthermore, the invention relates to an apparatus and a process for operating such a circuit arrangement.

Abstract: The invention relates to integrated circuits comprising a monolithically integrated logic IC and a monolithically integrated interface circuit that is conductively connected to the logic IC. The electrical properties of said interface circuit are programmable. The interface circuit also has a lower integration density than the logic IC, and comprises monitoring modules for monitoring the logic ICs.

Abstract: A monolithic sensor arrangement includes a housing, a sensor integrated in the housing, and two or three connecting contacts deployed on the housing so as to provide a contact with the sensor. The housing also includes an integrated digital circuit includes a freely programmable digital processor, a program memory and a data memory, which are used to control and/or process the functionalities and/or the measured data of the sensor.

Abstract: The invention relates to a circuit configuration with a serial test interface (TIF) to control a test operation mode, a freely programmable digital processor (CPU), a housing (G) for the accommodation of a test interface (TIF) and the processor (CPU) with terminals or connectors (C0, C1) for data and/or signal exchange with external components and setups. At one of the terminals (C1), a modulated supply voltage (VDD) can be received the transfer of data (d) and or a clock (T) by using at least two voltage levels (V2, V3) that can be controlled and which are different from a supply voltage level (V1) that is designed to feed the circuitry with a supply operating voltage. Furthermore, the invention relates to a serial test operation method for such a circuit configuration.

Abstract: An error correction and/or error detection method reads of stored information data from a storage device; wherein in addition to the information data, code data is read from the storage device. Syndrome data is formed from the information data and the code data in order to determine errors and/or error positions in the read data. For detection of multiple errors, it is verified whether in the case of a determined error position, the information data or code data associated with the relevant storage positions are either all equal to 0, or are all equal to 1.

Abstract: A network processor exchanges data of various descriptions via a plurality of network nodes with external network devices, such as other processors, controllers, transducers, or sensors. The network processor includes a master processor for control tasks of the processor, and a network coprocessor for supporting network tasks. A first and a second bus system, associated with the master processor and the network coprocessor with its associated functional units, particularly Data Link Layer memory devices, respectively, serves to separate the two fields of tasks from each other. This permits both a support of gateway functions and a support of Higher Layer functions. Higher Layer memory devices, whose messages are ultimately sent or received by the master processor, are accessible from the master processor or the network coprocessor directly or indirectly via the first and/or second bus systems.

Abstract: The invention relates to a method and a corresponding device for controlling a memory access, wherein a number of waiting states is established for the memory access to a storage device (FLASH/ROM, RAM, IO module) for a central control unit (CPU). A memory access is made possible in that the number of waiting states for the memory access is established individually as a function of an analysis of an instantaneous state (status) of the central control unit (CPU) and/or a type and/or address of the storage device (FLASH/ROM, RAM, IO module) being accessed.

Abstract: The invention relates to an interrupt controller (1) for controlling the access of interrupt sources (11, 12, 13, 14) to a processor (100) and for controlling the associated program branching of the signal processing being currently executed with a current priority (Px) in the processor. The input side of the interrupt controller (1) contains a specified number of interrupt interfaces (21, 22, 23, 24) for connecting the interrupt sources, a priority value (Pi) and an address (Adi) being allocated to each interrupt interface (21, 22, 23, 24). A selection device (30) determines which among the activated interrupt interfaces has the highest priority value (Pmax).

Abstract: The invention relates to a circuit arrangement and to a method for creating and retrieving replacement data. The circuit arrangement has a programmed ROM, which is coupled to a patch-memory module through an address and data bus. The patch-memory module has a plurality of patch-data registers and patch-address registers, in which the addresses and replacement data are stored. The invention makes it possible that a hard-wired and thus irreversibly programmed ROM can be modified and corrected by an external circuit arrangement. For example, erroneous instructions of program sequences and data can be replaced by error correction instructions during a ROM access of the program-controlled unit. By using dedicated registers, the RAM essentially can be dispensed with for error correction, while retaining the retrieval speed.

Abstract: The invention relates to a circuit arrangement and to a method for creating and retrieving replacement data. The circuit arrangement has a programmed ROM, which is coupled to a patch-memory module through an address and data bus. The patch-memory module has a plurality of patch-data registers and patch-address registers, in which the addresses and replacement data are stored. The invention makes it possible that a hard-wired and thus irreversibly programmed ROM can be modified and corrected by an external circuit arrangement. For example, erroneous instructions of program sequences and data can be replaced by error correction instructions during a ROM access of the program-controlled unit. By using dedicated registers, the RAM essentially can be dispensed with for error correction, while retaining the retrieval speed.