Abstract: Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer.

Abstract: The invention relates to a method and a system for placing electric circuits in integrated circuit chip design. Specifically, the invention encompasses performing a global placement step placing the cells into bins on the chip, as well as a detailed placement process which arranges the cells in the bins to obtain a legal arrangement while generating simply connected free space for routing channels.

Abstract: A computer readable medium, system and associated method is provided for designing an integrated circuit with inserted loops. The method comprises the steps of inserting a loop with tagged wire segments and/or vias in a fully routed and DCR clean integrated circuit; performing a DRC; and fixing DRC violations by removing tagged wire segments and/or vias which contribute to a violation.

Abstract: A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

Abstract: A method to reduce the problem complexity maintains a relatively high quality port assignment by abstracting local connections in the macro when performing the port assignment. This is done for netlength, congestion as well as timing. The internal netlist of the macro is abstracted in such a way that the optimization of the external interconnect can be done in an efficient manner. Three levels of abstractions are described. A first level optimizes the top level interconnect, a second level optimizes the top level and macro interconnects, while a third level optimizes the top level timing.

Abstract: In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.

Abstract: An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and Fourth wires form a path between the first and second wires redundant to the first via.

Abstract: In consideration for the fact that a connection on the upper layers of an integrated circuit needs to access a lower layer to connect to, e.g., a transistor, at least one via on each layer is required below the top layer used by a connection for each pin. The vias (i.e., the connection structures between wiring planes within an integrated circuit) are arranged such that the number of wiring resources blocked on the lower layers is reduced. Various rules govern which vias are chosen. The main characteristic is to elect only a certain number of wiring channels appropriate for the vias on a single layer and then apply an optimization within the restricted elected wiring channels on that layer to select the most appropriate vias.

Abstract: A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

Abstract: A method for generating a layout for an integrated circuit having a plurality of sinks and at least one source is disclosed. The source supplies a plurality of signals to the respective plurality of sinks. The method includes: identifying the source which supplies at least one of the respective sinks and having a negative slack; finding all sinks having a negative slack driven by the source; clustering the sinks according to timing and placement information read from a database, yielding a plurality of clusters of sinks, in which each cluster includes only a predetermined portion of the plurality of sinks; generating a plurality of clones associated with a respective one of the clusters of sinks; and coupling the clones to respective ones of the clusters of sinks yielding a second layout.

Abstract: A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

Abstract: A method for rerouting a wire in an integrated circuit includes determining a wire coupling a first circuit element to a second circuit element is experiencing capacitive coupling effects with one or more other wires; removing the wire from a netlist; dividing the structure into a routing grid; defining a first and second wire types; associating a penalty with each wire type; determining all possible paths through the routing grid between the first circuit element and the second circuit element; determining a weighted length for each path; and selecting the path having the lowest weighted length.

Abstract: A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.

Abstract: A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

Abstract: A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.

Abstract: A method to reduce the problem complexity maintains a relatively high quality port assignment by abstracting local connections in the macro when performing the port assignment. This is done for netlength, congestion as well as timing. The internal netlist of the macro is abstracted in such a way that the optimization of the external interconnect can be done in an efficient manner. Three levels of abstractions are described. A first level optimizes the top level interconnect, a second level optimizes the top level and macro interconnects, while a third level optimizes the top level timing.

Abstract: In consideration for the fact that a connection on the upper layers of an integrated circuit needs to access a lower layer to connect to, e.g., a transistor, at least one via on each layer is required below the top layer used by a connection for each pin. The vias (i.e., the connection structures between wiring planes within an integrated circuit) are arranged such that the number of wiring resources blocked on the lower layers is reduced. Various rules govern which vias are chosen. The main characteristic is to elect only a certain number of wiring channels appropriate for the vias on a single layer and then apply an optimization within the restricted elected wiring channels on that layer to select the most appropriate vias.

Abstract: A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

Abstract: A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed.

Abstract: A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.