Abstract: The present invention relates to a method for routing data paths in a semiconductor chip with a plurality of layers. The inventive method comprises the steps of wiring a launching clock path and a receiving clock path on one or more layers according to at least one predetermined condition, performing one or more timing tests for determining any critical paths, and determining a weight function for every layer of each critical path. Said weight function is defined as the difference between a property of the launching clock tree and the same property of the receiving clock tree on said layer. If said weight function is positive for any layer, the wiring of the data path is not allowed on said layer. Preferably the remaining layers are chosen in such a way that a local variation of the delay on said layer is minimal.

Abstract: The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. Said method comprises the steps of providing (10) a VHDL description of the digital circuit design, performing (12) a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating (14) a netlist including the elements of the digital circuit design and the connections between said elements. Said method comprises the further steps of providing (28) a transformation script with at least one transparent storage element (40; 54), wherein said transparent storage element (40; 54) represents a path delay within the digital circuit design, creating (30) a new netlist with the at least one transparent storage elements (40; 54), running (20) a verification, and checking, if the new netlist is clean from a logical and timing point of view.

Abstract: A method to provide optimization between synthesis and layout in modern integrated circuit design, the method includes the steps of: a) identifying (210) a source (10) which has at least one associated sink (30) having a negative slack, i.e. the source having a negative slack at its output; b) finding all sinks (30) driven by the identified source; and c) clustering (240) the sinks (30) according to timing and placement information read from a database, yielding a plurality of clusters (30a, 30b) of sinks, in which a cluster includes only a predetermined portion of the sinks.

Abstract: A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

Abstract: The present invention relates to creating a layout of an electronic circuit from a netlist of interconnected components, wherein the components can be represented by planar geometric shapes in the layout. The advantages of the present invention are achieved by tightly coupling placement and routing. An initial placement of shapes of extended size is succeeded by a routing step that tries to create wires between shapes of reduced size. If that fails, it is tried to wire shapes of extended size instead. The wiring can be combined with a delta-placement of shapes within shapes of extended size such that wires connected to shapes of extended size also connect to the shapes.

Abstract: A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed.

Abstract: A computer readable medium, system and associated method is provided for designing an integrated circuit with inserted loops. The method comprises the steps of inserting a loop with tagged wire segments and/or vias in a fully routed and DCR clean integrated circuit; performing a DRC; and fixing DRC violations by removing tagged wire segments and/or vias which contribute to a violation.

Abstract: The invention relates to a delay calculation method for wiring nets of an electronic circuit, wherein a net within an electronic circuit comprises a driver pin (P0; P30) and a receiving pin (P1-P19; P32-P42) being coupled by at least one loop (40, 50; 60, 70, 80), said loop (40, 50; 60, 70, 80) comprising a first branching path (BP40a, BP50a) and a second branching path (BP40b, BP50b) electrically parallel to said first branching path (BP40a, BP50a), wherein at least a first and a second branching point (I, OP10; P30, OP1, P42) connect said branching paths (BP40a, BP40b; BP50a, BP50b).

Abstract: The invention relates to a method and a system for placing electric circuits in integrated circuit chip design. Specifically, the invention encompasses performing a global placement step (112) placing the cells (11) into bins (12, 14, 16A, 16B) on the chip (10), as well as a detailed placement process (116) which arranges the cells in the bins (12, 14, 16A, 16B) to obtain a legal arrangement while generating simply connected free space (21, 21A, 21B) for routing channels (18?, 26).

Abstract: A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), Which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal, of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.

Abstract: A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

Abstract: A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

Abstract: Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer.

Abstract: Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the structural identifiers include wire codes, tags, and/or unique identifiers. Different structural identifiers are established for wires having different widths. Furthermore, the method establishes a weighting factor for each structure-specific mechanism, wherein higher weighting factors are established for structure-specific mechanisms comprising thick wires proximate to multiple thick wires. The method establishes the structural identifiers and the weighting factors for incidence of spacing between single wide lines, double wide lines, and triple wide lines and for incidence of wires above large metal lands.

Abstract: An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and Fourth wires form a path between the first and second wires redundant to the first via.

Abstract: A method of routing an interconnect metal layer of an integrated circuit, wherein single-width nets are replicated and routed in parallel to reduce the total resistance on the net; wide wires are decomposed into a several single-width wires routed in parallel to improve uniformity of metal interconnect routing and therefore manufacturability of metal interconnect layers. The decomposition step is performed during a preliminary wire route after initial physical placement. Access to pin shapes is ensured through a branching and a recombination of the parallel single-width wires. Separate wire segments are rejoined at the source and sink of the net. The parallel wire segments do not change the logic behavior of the circuit.

Abstract: Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer.

Abstract: An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

Abstract: The present invention relates to a method for designing fan-out nets connecting a signal source and a plurality of net elements in an integrated circuit. In order to make fan-out nets more robust against opens while keeping the risk due to short circuits in an acceptable degree, the method comprises the steps of: a) implementing a routing section in a closed structure comprising a plurality of signal receiving pins, wherein said receiving pins connect to further net elements, b) implementing on said closed structure a plurality of buffer elements to provide multiple signals derived from said source signal for driving said plurality of net elements, and c) limiting the distance and number of receiving cells between two buffer elements below predetermined values in order to keep a short circuit current given in case of an open tolerably small and within a worst case skew time delay.

Abstract: A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/or preceding sub tree.