Abstract: The present invention relates to a composition suitable for cosmetic applications, especially suitable for styling hair or for skin care purposes, comprising at least two of the components konjac gum, xanthan gum and algin, wherein the weight ratios of these components are within a specified range. Furthermore, the present invention relates to a raw material composition consisting of at least two of the said components, wherein this raw material composition can be used to make the composition according to the present invention. Furthermore, the present invention relates to the use of the composition for styling hair or for skin care.

Abstract: A coating, preferably a color coating, method for keratin fibers is described which includes three steps: activation, pretreatment and binding. The activation step includes one or both of a Praeparatur procedure and a Fundamenta procedure to produce modified fibers. The pretreatment step applies a pretreatment composition of at least a PTH alkoxysilane with PTH as a thiol, a protected thiol or a group complementarily reactive with thiol to the modified fibers to form pretreated fibers. The binding step applies a film forming composition to the pretreated fibers to form the color coating.

Abstract: The present invention relates to a composition suitable for cosmetic applications, especially suitable for styling hair or for skin care purposes, comprising at least two of the components konjac gum, tara gum and algin, wherein the weight ratios of these components are within a specified range. Furthermore, the present invention relates to a raw material composition consisting of at least two of the said components, wherein this raw material composition can be used to make the composition according to the present invention. Furthermore, the present invention relates to the use of the composition for styling hair or for skin care.

Abstract: A resolver-to-digital converter, comprising: a feedback (FB) filter chain loop having a state observer configured to estimate a rotation speed and a rotation angle of an object, based on a pair of input sine and cosine signals that are amplitude-modulated (AM) to correspond with the rotation angle of the object; and a feedforward (FF) filter chain path configured to estimate the rotation speed of the object based on the pair of input sine and cosine signals, wherein the state observer of the FB filter chain loop is further configured to offset the estimated rotation speed of the FB filter chain loop with the estimated rotation speed of the FF filter chain path to decrease a settling time of the estimated rotation angle.

Abstract: A device including at least one processor, and an analog-to-digital (ADC) circuit, wherein the at least one processor is configured to generate an excitation signal and provide the excitation signal to a crystal in a pierce oscillation configuration, wherein after providing the excitation signal, the ADC circuit is configured to obtain as input a signal output from the crystal and convert the signal to a digital output; the at least one processor is configured to compare the digital output of the ADC circuit to a plurality of thresholds and based on the comparisons is further configured to drive the crystal to cause the crystal to operate as a pierce oscillator and to generate a clock signal from at least of one of the comparisons.

Abstract: A resolver-to-digital converter, comprising: a feedback (FB) filter chain loop having a state observer configured to estimate a rotation speed and a rotation angle of an object, based on a pair of input sine and cosine signals that are amplitude-modulated (AM) to correspond with the rotation angle of the object; and a feedforward (FF) filter chain path configured to estimate the rotation speed of the object based on the pair of input sine and cosine signals, wherein the state observer of the FB filter chain loop is further configured to offset the estimated rotation speed of the FB filter chain loop with the estimated rotation speed of the FF filter chain path to decrease a settling time of the estimated rotation angle.

Abstract: A device including at least one processor, and an analog-to-digital (ADC) circuit, wherein the at least one processor is configured to generate an excitation signal and provide the excitation signal to a crystal in a pierce oscillation configuration, wherein after providing the excitation signal, the ADC circuit is configured to obtain as input a signal output from the crystal and convert the signal to a digital output; the at least one processor is configured to compare the digital output of the ADC circuit to a plurality of thresholds and based on the comparisons is further configured to drive the crystal to cause the crystal to operate as a pierce oscillator and to generate a clock signal from at least of one of the comparisons.

Abstract: According to various embodiments, a circuit for determining the frequency of a signal is described, comprising an input configured to receive an analog input signal, an analog to digital converter configured to convert the analog input signal to a digital input signal, a digital mixer configured to generate a mixing result signal by mixing the digital input signal with a single bit binary signal having a reference frequency, a low pass filter configured to generate a filtered signal by filtering the mixing result signal, a measuring circuit configured to measure the period of the filtered signal and an output configured to output a value differing from the frequency of the single bit binary signal by the inverse of the measured period as the frequency to be determined.

Abstract: A calibration circuit, including: a signal generator circuit configured to generate a modulated analog input signal, which is based on a digital input word that is modulated; an Analog-to-Digital Converter (ADC) configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and a feedback circuit configured to output the digital input word by adjusting the digital calibration word depending on a digital feedback signal, which is based on a modulated version of the analog reference signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip.

Abstract: A method for determining the dryness of a fibrous web, in particular a tissue web, during the production of the fibrous web, is carried out in a machine including a drying cylinder, in particular a Yankee cylinder, to which at least one, preferably two, dryer hoods are assigned, and a reel-up for winding up the fibrous web. The determination of the dryness of the fibrous web is carried out before the drying cylinder on the basis of measured values which describe the following variables: the amount of solids in the fiber web at the reel-up, the amount of water in the fiber web at the reel-up, and the amount of water which is evaporated in the dryer hood or hoods. A method for controlling or regulating a machine for producing a fibrous web, a computer program and computer program product are also provided.

Abstract: Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.

Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.

Abstract: An analog-to-digital device includes a sampling circuit for sampling an input signal. The sampling circuit stops sampling in response to obtaining a trigger signal. The analog-to-digital device includes an analog-to-digital converter circuit which includes an analog to digital converter (ADC) for converting a sampled input provided from the sampling circuit to digital output.

Abstract: Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.

Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.

Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

Abstract: A system for executing an artificial neural network having a plurality of interconnected nodes, the system includes a memory storing weight values of the neural network. The memory can be configured to a store node value and a mask bit value for each of the plurality of nodes of the neural network. Further the system can include multiply and accumulate (MAC) units to perform operations for determining node values. The system includes a control unit circuitry that, during execution of the neural network, dynamically controls operations of the MAC units to cause a reduction in a number of calculations to be performed by the MAC units. The control unit circuitry causes the MAC units to perform operations involving a subset of the plurality of nodes to avoid performing operations involving nodes of the plurality nodes that are outside of the subset.

Abstract: A calibration circuit, including: a signal generator circuit configured to generate a modulated analog input signal, which is based on a digital input word that is modulated; an Analog-to-Digital Converter (ADC) configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and a feedback circuit configured to output the digital input word by adjusting the digital calibration word depending on a digital feedback signal, which is based on a modulated version of the analog reference signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip.

Abstract: A calibration circuit, including: a first analog-to-digital converter (ADC) configured to sample a nonlinear reference signal continuously at an equidistant sampling rate to generate a reference sampled signal; a trigger timer configured to generate trigger signals; a second ADC configured to sample a point of each of the nonlinear reference signal and repeated versions of the nonlinear reference signal in response to the respective trigger signals at equidistantly increasing delays, to generate a device-under-test (DUT) sampled voltage; and processing circuitry configured to estimate a differential nonlinearity (DNL) of the DUT sampled signal, estimate a DNL of the reference sampled signal, and compare the estimated DNL of the DUT sampled signal with the estimated DNL of the reference sampled signal, to generate a DNL performance indication signal of the second ADC.

Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.