Patents by Inventor Jürgen Schäfer

Jürgen Schäfer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11526389
    Abstract: A fault check circuit, including a first channel comparator to output a first channel comparator output signal indicating whether a first channel digital signal is outside of a first channel threshold range, wherein the first channel digital signal is A/D converted from a first channel analog signal; a second channel comparator to output a second channel comparator output signal indicating whether a second channel digital signal is outside of a second channel threshold range, wherein the second channel digital signal is A/D converted from a second channel analog signal; and an alarm generator circuit to combine the first and second channel comparator output signals, and output a fault check signal, wherein the first and second channel comparators and the alarm generator circuit are implemented in hardware, and the fault check circuit performs a fault check without software intervention.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: December 13, 2022
    Assignee: Infineon Technologies AG
    Inventors: Ketan Dewan, Juergen Schaefer
  • Patent number: 11512017
    Abstract: In known methods for producing a glass component, a void-containing intermediate product containing doped or non-doped SiO2 is inserted into a sheath tube composed of glass, which has a longitudinal axis and an inner bore, and is thermally treated therein. In order to subject the intermediate product to a thermal and/or reactive treatment that is reproducible and uniform in its effect from this starting point, it is proposed in one embodiment that into the sheath tube's inner bore a first gas-permeable gas diffuser is inserted which is displaceable along the sheath tube's longitudinal axis and is pressed against the intermediate product during the thermal treatment.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 29, 2022
    Assignee: Heraeus Quarzglas GmbH & Co. KG
    Inventors: Jacqueline Plass, Dörte Schönfeld, Clemens Schmitt, Alexander Laaz, Andreas Langner, Gerhard Schötz, Walter Lehmann, Michael Hünermann, Stefan Weidlich, Jürgen Schäfer
  • Publication number: 20220276323
    Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.
    Type: Application
    Filed: May 9, 2022
    Publication date: September 1, 2022
    Inventors: Ketan Dewan, Rocco Calabro, Juergen Schaefer
  • Patent number: 11416301
    Abstract: A data processing device is provided.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: August 16, 2022
    Assignee: Infineon Technologies AG
    Inventors: Konrad Walluszik, Juergen Schaefer
  • Publication number: 20220179012
    Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 9, 2022
    Inventors: Ketan Dewan, Rocco Calabro, Juergen Schaefer
  • Patent number: 11353517
    Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: June 7, 2022
    Assignee: Infineon Technologies AG
    Inventors: Ketan Dewan, Rocco Calabro, Juergen Schaefer
  • Publication number: 20220166442
    Abstract: An analog-to-digital device includes a sampling circuit for sampling an input signal. The sampling circuit stops sampling in response to obtaining a trigger signal. The analog-to-digital device includes an analog-to-digital converter circuit which includes an analog to digital converter (ADC) for converting a sampled input provided from the sampling circuit to digital output.
    Type: Application
    Filed: November 23, 2021
    Publication date: May 26, 2022
    Inventors: Ketan Dewan, Rocco Calabro, Juergen Schaefer, David Schaffenrath
  • Patent number: 11329608
    Abstract: Systems, methods, and circuits are provided for facilitating negative resistance margin testing in an oscillator circuit. An example oscillator circuit includes amplifier circuitry configured to be coupled in parallel with a resonator and variable resistance circuitry configured to, in response to a resistance control signal, adjust a resistance of the oscillator circuit.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies AG
    Inventors: Mihail Jefremow, Rex Kho, Ralph Mueller-Eschenbach, Juergen Schaefer, Arndt Voigtlaender, Wei Wang
  • Publication number: 20220131499
    Abstract: Systems, methods, and circuits are provided for facilitating negative resistance margin testing in an oscillator circuit. An example oscillator circuit includes amplifier circuitry configured to be coupled in parallel with a resonator and variable resistance circuitry configured to, in response to a resistance control signal, adjust a resistance of the oscillator circuit.
    Type: Application
    Filed: October 23, 2020
    Publication date: April 28, 2022
    Inventors: Mihail Jefremow, Rex Kho, Ralph Mueller-Eschenbach, Juergen Schaefer, Arndt Voigtlaender, Wei Wang
  • Publication number: 20220085824
    Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.
    Type: Application
    Filed: September 7, 2021
    Publication date: March 17, 2022
    Inventors: Mihail Jefremow, Ketan Dewan, Rex Kho, Ralph Mueller-Eschenbach, Juergen Schaefer
  • Publication number: 20210382776
    Abstract: A fault check circuit, including a first channel comparator to output a first channel comparator output signal indicating whether a first channel digital signal is outside of a first channel threshold range, wherein the first channel digital signal is A/D converted from a first channel analog signal; a second channel comparator to output a second channel comparator output signal indicating whether a second channel digital signal is outside of a second channel threshold range, wherein the second channel digital signal is A/D converted from a second channel analog signal; and an alarm generator circuit to combine the first and second channel comparator output signals, and output a fault check signal, wherein the first and second channel comparators and the alarm generator circuit are implemented in hardware, and the fault check circuit performs a fault check without software intervention.
    Type: Application
    Filed: June 3, 2020
    Publication date: December 9, 2021
    Inventors: Ketan Dewan, Juergen Schaefer
  • Patent number: 11177987
    Abstract: Processing a resolver signal by a microcontroller includes generating, by a carrier signal generator, a carrier signal for output to a resolver; receiving modulated carrier signals from a resolver via hardware that is external to the microcontroller; integrating, by an integrator, respective integrator input signals which are based on the modulated carrier signals, to generate respective envelope signals, wherein a start of an integration window of the integrator is set with respect to a start of the carrier signal; and determining an angular position sensed by the resolver based on the envelope signals.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 16, 2021
    Assignee: Infineon Technologies AG
    Inventors: Mihail Jefremow, Michael Augustin, Ketan Dewan, Ralph Mueller-Eschenbach, Juergen Schaefer
  • Publication number: 20210248013
    Abstract: A data processing device is provided.
    Type: Application
    Filed: February 4, 2021
    Publication date: August 12, 2021
    Inventors: Konrad Walluszik, Juergen Schaefer
  • Patent number: 10947284
    Abstract: The present invention relates to fusion molecules that have binding specificity for pyoverdine type I, II and III and pyochelin and can be used in various applications, including diagnostic and/or therapeutic applications, for example, to inhibit or reduce growth of P. aeruginosa and/or to prevent or treat P. aeruginosa biofilm infection as well as diseases or disorders associated with P. aeruginosa biofilm infection. The present invention also concerns methods of producing the fusion molecules described herein as well as compositions and kits comprising such fusion molecules. The present invention further relates to nucleic acid molecules encoding the fusion molecules described herein.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: March 16, 2021
    Assignee: Pieris Pharmaceuticals GmbH
    Inventors: Carsten Corvey, Heike Stump, Jochen Kruip, Christian Lange, Ingo Focken, Dorothea Rat, Thomas Stuedemann, Hans-Falk Rasser, Juergen Schaefer, Bernard Calandra, Astrid Rey, Michael Mourez, Laurent Fraisse, Christine Rothe, Andrea Allersdorfer, Alexander Wiedenmann, Marlon Hinner, Bradley Lunde, Kristian Jensen, Martin Hülsmeyer
  • Publication number: 20200385927
    Abstract: A method for determining the dryness of a fibrous web, in particular a tissue web, during the production of the fibrous web, is carried out in a machine including a drying cylinder, in particular a Yankee cylinder, to which at least one, preferably two, dryer hoods are assigned, and a reel-up for winding up the fibrous web. The determination of the dryness of the fibrous web is carried out before the drying cylinder on the basis of measured values which describe the following variables: the amount of solids in the fiber web at the reel-up, the amount of water in the fiber web at the reel-up, and the amount of water which is evaporated in the dryer hood or hoods. A method for controlling or regulating a machine for producing a fibrous web, a computer program and computer program product are also provided.
    Type: Application
    Filed: November 20, 2018
    Publication date: December 10, 2020
    Inventors: JAN ACHTERMANN, MARCUS SCHWIER, MARCO POPP, JUERGEN SCHAEFER
  • Patent number: 10848354
    Abstract: A measurement apparatus for providing digital data to a controller, including an Analog-to-Digital Converter (ADC) configured to transform an analog signal into a modulated digital data stream; an event detector configured to generate event indication data based on an event related to the analog signal or the digital data; and a communication interface configured to combine the modulated digital data stream and the event indication data into one or more communication frames, and to transmit the one or more communication frames to the controller.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: November 24, 2020
    Assignee: Infineon Technologies AG
    Inventors: Jens Barrenscheen, Juergen Schaefer
  • Patent number: 10816642
    Abstract: In various embodiments, a circuitry configured to generate a voltage is provided. The circuitry may include a sequence generator configured to provide a sequence of data words consisting of bits. The number of bits is greater than two. The circuitry may further include a delta-sigma modulator configured to receive the sequence of data words provided by the sequence generator and to provide a delta-sigma modulated first single bit data stream at a first data rate, and a decimation filter configured to generate a stream of decimated data words from the first single bit data stream at a second data rate. The second data rate may be smaller than the first data rate, each decimated data word including a plurality of bits. The circuitry may further include a parallel-to-serial converter configured to convert the decimated data words to a second single bit data stream while preserving the second data rate.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 27, 2020
    Assignee: Infineon Technologies AG
    Inventors: Ketan Dewan, Reinhard Kussian, Juergen Schaefer
  • Publication number: 20200277217
    Abstract: In known methods for producing a glass component, a void-containing intermediate product containing doped or non-doped SiO2 is inserted into a sheath tube composed of glass, which has a longitudinal axis and an inner bore, and is thermally treated therein. In order to subject the intermediate product to a thermal and/or reactive treatment that is reproducible and uniform in its effect from this starting point, it is proposed in one embodiment that into the sheath tube's inner bore a first gas-permeable gas diffuser is inserted which is displaceable along the sheath tube's longitudinal axis and is pressed against the intermediate product during the thermal treatment.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 3, 2020
    Applicant: Heraeus Quarzglas GmbH & Co. KG
    Inventors: Jacqueline Plass, Dörte Schönfeld, Clemens Schmitt, Alexander Laaz, Andreas Langner, Gerhard Schötz, Walter Lehmann, Michael Hünermann, Stefan Weidlich, Jürgen Schäfer
  • Publication number: 20200076655
    Abstract: A measurement apparatus for providing digital data to a controller, including an Analog-to-Digital Converter (ADC) configured to transform an analog signal into a modulated digital data stream; an event detector configured to generate event indication data based on an event related to the analog signal or the digital data; and a communication interface configured to combine the modulated digital data stream and the event indication data into one or more communication frames, and to transmit the one or more communication frames to the controller.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 5, 2020
    Inventors: Jens Barrenscheen, Juergen Schaefer
  • Publication number: 20190382455
    Abstract: The present invention relates to fusion molecules that have binding specificity for pyoverdine type I, II and III and pyochelin and can be used in various applications, including diagnostic and/or therapeutic applications, for example, to inhibit or reduce growth of P. aeruginosa and/or to prevent or treat P. aeruginosa biofilm infection as well as diseases or disorders associated with P. aeruginosa biofilm infection. The present invention also concerns methods of producing the fusion molecules described herein as well as compositions and kits comprising such fusion molecules. The present invention further relates to nucleic acid molecules encoding the fusion molecules described herein.
    Type: Application
    Filed: April 24, 2019
    Publication date: December 19, 2019
    Inventors: Carsten Corvey, Heike Stump, Jochen Kruip, Christian Lange, Ingo Focken, Dorothea Rat, Thomas Stuedemann, Hans-Falk Rasser, Juergen Schaefer, Bernard Calandra, Astrid Rey, Michael Mourez, Laurent Fraisse, Christine Rothe, Andrea Allersdorfer, Alexander Wiedenmann, Marlon Hinner, Bradley Lunde, Kristian Jensen, Martin Hülsmeyer