Abstract: Method and apparatus for providing a wireless mesh network and network node are described. More particularly, a network having network node neighborhoods is described. A node comprises a multi-sectored antenna and a transceiver controller. Nodes are configured for installation without antenna pointing and without pre-coordination with the network. Software architecture for the node is also described.

Abstract: Method, system and computer program product for verifying the address generation, address generation interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values from a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second set of general purpose register values on a bus.

Abstract: A bodyweight resistance exercise apparatus has a base portion, a platform secured to the base portion, main vertical supports coupled to an end of the base portion, upper vertical supports coupled to an upper end of the main vertical supports and angled relative thereto, and lifting straps coupled through the upper vertical supports and to the main vertical supports. Adjustability may be provided in a number of ways, including with respect to the location of the platform along the base portion, the angle of the main vertical supports relative to the base portion, the rotational position of the upper vertical supports relative to the main vertical supports, and the attachment of the lifting straps along the main vertical supports. When a desired configuration is achieved, a user may perform bodyweight resistance exercise in a core-stabilized position.

Abstract: A digital tuning system (250) for changing a cutoff frequency of an analog filter (132) includes digital synthesizers (292 and 294) for producing a two-tone calibration signal (196) applied to an input of the filter after a quality factor of the filter is increased. The filter includes at least one R/C circuit with two resistors (304 and 306) for changing the quality factor and arrays (308 and 310) of capacitors for changing the cutoff frequency. The amplitude of the magnitude responses (409 and 411) of the filter to each tone (405 and 407) is measured by a two discrete Fourier transform single-frequency bin power detection circuits (253 and 254) while the filter is sequenced through a plurality of capacitance settings. An optimal capacitance for the R/C circuit is selected by comparing, to a pre-selected value, a difference between the responses of the filter to each tone, for each capacitance setting.

Abstract: Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on synchronous clock boundaries. Further, data is exchanged across the network on latch boundaries. Thus, management aspects of the simulation, such as management associated with the global simulation time, are simplified.

Abstract: Method and apparatus for providing a wireless mesh network and network node are described. More particularly, a network having network node neighborhoods is described. A node comprises a multi-sectored antenna and a transceiver controller. Nodes are configured for installation without antenna pointing and without pre-coordination with the network. Software architecture for the node is also described.

Abstract: A device for testing a data carrying service operating over a telecommunications line includes a plurality of test circuits. Each test circuit is arranged to determine and test one or more characteristics of a data carrying service and a termination of the telecommunications line is emulated. The operation of each of the plurality of test circuits is controlled, and the telecommunications lines is connected to one or more of the plurality of test circuits. The data carrying service remains connected via a connection during all of the testing operations provided by one or more of the test circuits which enables the device to automatically determine the identity of the data carrying service. The test circuits may be arranged to enable emulation of a termination to be interconnected so as to enable the device to provide a passive link in the data carrying service and/or provide throughput testing of the telecommunications line.

Abstract: Method, system and computer program product for verifying the address generation, address generation, interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values fern a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second, set of general purpose register values on a bus.

Abstract: A device for testing a data carrying service operating over a telecommunications line includes a plurality of test circuits. Each test circuit is arranged to determine and test one or more characteristics of a data carrying service and a termination of the telecommunications line is emulated. The operation of each of the plurality of test circuits is controlled, and the telecommunications lines is connected to one or more of the plurality of test circuits. The data carrying service remains connected via a connection during all of the testing operations provided by one or more of the test circuits which enables the device to automatically determine the identity of the data carrying service. The test circuits may be arranged to enable emulation of a termination to be interconnected so as to enable the device to provide a passive link in the data carrying service and/or provide throughput testing of the telecommunications line.

Abstract: A wireless mesh communication protocol that dynamically assigns communication time-slots and frequencies to mesh nodes. A first node is established as a PC that sequentially polls other nodes. A second node responds at a predetermined time with information that includes database records, and then a third node responds similarly. The second node is then established as the PC and the first node is polled during dynamically allocated time-slots and on a frequency that depend on the second node's database records. The third node is then established as a PC and acts similarly. In both cases the first node responds by sending information and data records. The first node is then re-established as the PC. The first node then polls the second and third nodes at times and frequencies that depend on the first node's database records.

Abstract: Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on synchronous clock boundaries. Further, data is exchanged across the network on latch boundaries. Thus, management aspects of the simulation, such as management associated with the global simulation time, are simplified.

Abstract: Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on synchronous clock boundaries. Further, data is exchanged across the network on latch boundaries. Thus, management aspects of the simulation, such as management associated with the global simulation time, are simplified.

Abstract: A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes providing a plurality of selection devices for selecting initialization data to store in the plurality of latches of the IC's boundary latch module. The initialization data is selected from a plurality of scan paths of the integrated circuit, and the initialization data from at least one of the latches is provided as input to a logic circuit of the IC or output of the IC. In another aspect, the method includes selecting a datum from an external input or test-pattern generator of the integrated circuit for capture in at least one of the latches and input to a multiple-input signature register, which stores a signature of the integrated circuit resulting from the logic built-in self-testing.

Abstract: A solution for matching RADIUS request packets with corresponding RADIUS response packets when the number of simultaneous outstanding requests is greater than 256 involves using a sixteen-octet authenticator field in each packet. For each response packet that arrives, the identifier of the packet is compared in turn with the identifier of each outstanding request packet. If the identifiers match, the authenticators are then compared. If the results of the comparison indicate a match, the packet is accepted and no further processing of the outstanding requests is required. Otherwise, a search of the outstanding request packets is continued. This solution allows for more than 256 simultaneous outstanding RADIUS requests and only encounters a mismatch or ambiguous match with a probability of one in 3.4×1038 packets.

Abstract: A technique is provided for simultaneous and/or selective self-testing of internal logic and asynchronous boundaries of an IC having a plurality of clock domains. A clock command is generated by an on product clock generator for each clock domain simultaneously; and an asynchronous receive clock driver provides a programmable delay to a capture clock based on predetermined cycle requirements of the asynchronous boundaries. Asynchronous boundary test requirements are defined exclusively from the perspective of the asynchronous boundary receiver latches, thereby reducing dependencies among clock domains. Advantageously, the design of internal logic and asynchronous boundaries of each clock domain, ultimately residing within an IC, can proceed without a priori knowledge of how the clock domain will eventually be used in aggregation with other clock domains.

Abstract: A testing method is provided which includes verifying at least one external signal path of an electronic package environment by testing an input/output (I/O) circuit of an integrated circuit of the electronic package environment with a logic built-in self-test (LBIST) of the integrated circuit, wherein the external signal path being verified is electrically coupled to the tested I/O circuit. A result of verifying of the at least one external signal path is manifested in the integrated circuit's signature, which characterizes a response of the I/O circuit to the LBIST. In another aspect, the verifying of the at least one external signal path includes concurrently testing another I/O circuit of another integrated circuit, which is also electrically coupled to the external signal path.

Abstract: A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.

Abstract: A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.

Abstract: A digital tuning system (250) for changing a cutoff frequency of an analog filter (132) includes digital synthesizers (292 and 294) for producing a two-tone calibration signal (196) applied to an input of the filter after a quality factor of the filter is increased. The filter includes at least one R/C circuit with two resistors (304 and 306) for changing the quality factor and arrays (308 and 310) of capacitors for changing the cutoff frequency. The amplitude of the magnitude responses (409 and 411) of the filter to each tone (405 and 407) is measured by a two discrete Fourier transform single-frequency bin power detection circuits (253 and 254) while the filter is sequenced through a plurality of capacitance settings. An optimal capacitance for the R/C circuit is selected by comparing, to a pre-selected value, a difference between the responses of the filter to each tone, for each capacitance setting.

Abstract: Network channel access protocol is disclosed. More particularly, a distributed, locally determined, channel access protocol that adapts to load, avoids interference and controls access by a group of nodes to a set of shared channels is disclosed. Shared channel space is divided into a number of communication slots that are repeated at a predetermined interval. Permission to use a slot to communicate between any two nodes is dynamically adjusted by the channel access protocol, which locally: (i) estimates load to neighboring nodes; (ii) allocates or deallocates slot usage to adapt to load and avoid interference; and (iii) asserts and advertises slot usage within an interference area about itself.