Abstract: Network channel access protocol is disclosed. More particularly, a distributed, locally determined, channel access protocol that adapts to load, avoids interference and controls access by a group of nodes to a set of shared channels is disclosed. Shared channel space is divided into a number of communication slots that are repeated at a predetermined interval. Permission to use a slot to communicate between any two nodes is dynamically adjusted by the channel access protocol, which locally: (i) estimates load to neighboring nodes; (ii) allocates or deallocates slot usage to adapt to load and avoid interference; and (iii) asserts and advertises slot usage within an interference area about itself.

Abstract: A wireless mesh communication protocol that dynamically assigns communication time-slots and frequencies to mesh nodes. A first node is established as a PC that sequentially polls other nodes. A second node responds at a predetermined time with information that includes database records, and then a third node responds similarly. The second node is then established as the PC and the first node is polled during dynamically allocated time-slots and on a frequency that depend on the second node's database records. The third node is then established as a PC and acts similarly. In both cases the first node responds by sending information and data records. The first node is then re-established as the PC. The first node then polls the second and third nodes at times and frequencies that depend on the first node's database records.

Abstract: Network channel access protocol is disclosed. More particularly, a distributed, locally determined, channel access protocol that adapts to load, avoids interference and controls access by a group of nodes to a set of shared channels is disclosed. Shared channel space is divided into a number of communication slots that are repeated at a predetermined interval. Permission to use a slot to communicate between any two nodes is dynamically adjusted by the channel access protocol, which locally: (i) estimates load to neighboring nodes; (ii) allocates or deallocates slot usage to adapt to load and avoid interference; and (iii) asserts and advertises slot usage within an interference area about itself.

Abstract: A testing method is provided which includes verifying at least one external signal path of an electronic package environment by testing an input/output (I/O) circuit of an integrated circuit of the electronic package environment with a logic built-in self-test (LBIST) of the integrated circuit, wherein the external signal path being verified is electrically coupled to the tested I/O circuit. A result of verifying of the at least one external signal path is manifested in the integrated circuit's signature, which characterizes a response of the I/O circuit to the LBIST. In another aspect, the verifying of the at least one external signal path includes concurrently testing another I/O circuit of another integrated circuit, which is also electrically coupled to the external signal path.

Abstract: A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes providing a plurality of selection devices for selecting initialization data to store in the plurality of latches of the IC's boundary latch module. The initialization data is selected from a plurality of scan paths of the integrated circuit, and the initialization data from at least one of the latches is provided as input to a logic circuit of the IC or output of the IC. In another aspect, the method includes selecting a datum from an external input or test-pattern generator of the integrated circuit for capture in at least one of the latches and input to a multiple-input signature register, which stores a signature of the integrated circuit resulting from the logic built-in self-testing.

Abstract: A technique for distributed processing a partitioned model is provided based on tight functional coupling of multiple submodels of the model. The technique includes, in one embodiment, providing each submodel with a generic coupler to enable processing of the submodel on any simulator instance of any simulator. Submodels coupled with the generic couplers can be processed on the same or different computing units. The generic couplers facilitate communication between submodels through a common communication directory (CCD) by using functions of a generic coupler shared library. The generic couplers further use functions of the shared library to ensure integrity of data transmitted between submodels.

Abstract: Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on synchronous clock boundaries. Further, data is exchanged across the network on latch boundaries. Thus, management aspects of the simulation, such as management associated with the global simulation time, are simplified.

Abstract: Network channel access protocol is disclosed. More particularly, a distributed, locally determined, channel access protocol that adapts to load, avoids interference and controls access by a group of nodes to a set of shared channels is disclosed. Shared channel space is divided into a number of communication slots that are repeated at a predetermined interval. Permission to use a slot to communicate between any two nodes is dynamically adjusted by the channel access protocol, which locally: (i) estimates load to neighboring nodes; (ii) allocates or deallocates slot usage to adapt to load and avoid interference; and (iii) asserts and advertises slot usage within an interference area about itself.

Abstract: A scalable LBIST control structure provides for testing of multiple independent clock domains within a chip and/or across multiple chips. The LBIST control structure sequences all clock domains through each step of the LBIST sequence synchronously, allowing multiple clock domains and/or multiple chips to be controlled from a common point.

Abstract: At least a portion of the administrative responsibilities of one license server is transferred from the one license server to one or more other license servers. These responsibilities include the management of software licenses. This transfer is performed dynamically, such that vendor authorization, at the time of the transfer, is not needed. Further, the transfer of the administrative capabilities can occur prior to the expiration of the licenses being administered.

Abstract: A model is partitioned into a plurality of partitions to be processed by a selected number of processors. Since the partitions are substantially independent of one another, the policy employed in the mapping of the partitions to the processors is flexible. Further, in the case in which the model is a chip, at least a portion of the clock and maintenance logic of the chip is also partitioned and mapped to the selected number of processors.

Abstract: Network channel access protocol is disclosed. More particularly, a distributed, locally determined, channel access protocol that adapts to load, avoids interference and controls access by a group of nodes to a set of shared channels is disclosed. Shared channel space is divided into a number of communication slots that are repeated at a predetermined interval. Permission to use a slot to communicate between any two nodes is dynamically adjusted by the channel access protocol, which locally: (i) estimates load to neighboring nodes; (ii) allocates or deallocates slot usage to adapt to load and avoid interference; and (iii) asserts and advertises slot usage within an interference area about itself.

Abstract: A method and system select delay values from a VHDL standard delay file that correspond to an instance of a logic gate in a logic model. Then the system collects all the delay values of the selected instance and builds super generics for the rise-time and the fall-time of the selected instance. Then, the system repeats this process for every delay value in the standard delay file (310) that correspond to every instance of every logic gate in the logic model. The system then outputs a reduced size standard delay file (314) containing the super generics for every instance of every logic gate in the logic model.

Abstract: A computerized payment system and method is disclosed which provides subscribers with funds based on their income at regular, pre-defined intervals other than those on which they are normally paid. In so doing, it interfaces with the subscriber or with the subscriber and his source of income, and utilizes a computer network to electronically transfer funds and record transactions. Payments may be made with either net pay, or net pay less deductions; may be of advances or distributions; and may be of either fixed or variable amounts.

Abstract: A planar antenna that facilitates directional communication to a mesh network. The antenna is housed in a relatively small, planar package that can easily be attached to a window pane to enable the antenna to communicate with a neighboring rooftop mounted node of the mesh network. The package contains an M by N element phased array, where M and N are integers greater than one. The array is driven by microwave signals supplied from a P-angle phase shifting circuit, where P is an integer greater than one. Thus, the antenna synthesizes a single main beam and the antenna's main beam can be electrically “pointed” in one of P directions. In one embodiment of the invention, the array comprises 40 physical elements (8×5 elements) and has three selectable directions (i.e., the phase shifters provide +90, 0 and ?90 degree shifts that move the beam left 45 degrees, center and right 45 degrees).

Abstract: A resistor capacitor (RC) tracking loop includes a parasitic insensitive integrator (211) charged by a buffer (207) with offset compensation. The integrator (211) operates to provide an accurate ramped voltage proportional to a measured RC time constant. A single comparator (213) is used for sensing the voltage ramp rate by detecting two multiplexed reference voltages (VREFLO VREFHI). A timer within controller (201) is triggered by the VREFLO crossing at comparator (213). The timer counts the number of precision reference clock periods (FREF) that occur between the VREFLO and VREFHI crossings and adjusts an accumulator within controller (201) to a value (M). This value (M) is directly used to adjust a resistor and/or capacitor array used in a continuous time filter whose bandwidth and corner frequency can be precisely tuned.

Abstract: An adaptive analog-to-digital converter (ADC) system (100) includes an automatic gain control (AGC) controller (101) for receiving both in-band and out-of-band signals from a radio frequency (RF) receiver and producing an AGC control signal therefrom. A digital signal processor (DSP) (103) is then used for interpreting the AGC control signal and providing an adjustment signal to an ADC (105). The ADC (105) uses the adjustment signal to dynamically control efficiency of the ADC system 100 by adjusting bit resolution, reference capacitance and bias based upon the RF signal received and desired protocol requirements presented to the AGC controller (101).

Abstract: A planar antenna that facilitates directional communication to a mesh network. The antenna is housed in a relatively small, planar package that can easily be attached to a window pane to enable the antenna to communicate with a neighboring rooftop mounted node of the mesh network. The package contains an M by N element phased array, where M and N are integers greater than one. The array is driven by microwave signals supplied from a P-angle phase shifting circuit, where P is an integer greater than one. Thus, the antenna synthesizes a single main beam and the antenna's main beam can be electrically “pointed” in one of P directions. In one embodiment of the invention, the array comprises 40 physical elements (8×5 elements) and has three selectable directions (i.e., the phase shifters provide +90, 0 and −90 degree shifts that move the beam left 45 degrees, center and right 45 degrees).

Abstract: A method and system unbind a rise/fall tuple of a VHDL generic variable and create rise time and fall time generics of each generic variable that are independent of each other. Then, according to a predetermined correlation policy, the method and system collect delay values in a VHDL standard delay file, sort the delay values, remove duplicate delay values, group the delay values into correlation sets, and output an analysis file. The correlation policy may include collecting all generic variables in a VHDL standard delay file, selecting each generic variable, and performing reductions on the set of delay values associated with each selected generic variable.

Abstract: A solution for matching RADIUS request packets with corresponding RADIUS response packets when the number of simultaneous outstanding requests is greater than 256 involves using a sixteen-octet authenticator field in each packet. For each response packet that arrives, the identifier of the packet is compared in turn with the identifier of each outstanding request packet. If the identifiers match, the authenticators are then compared. If the results of the comparison indicate a match, the packet is accepted and no further processing of the outstanding requests is required. Otherwise, a search of the outstanding request packets is continued. This solution allows for more than 256 simultaneous outstanding RADIUS requests and only encounters a mismatch or ambiguous match with a probability of one in 3.4×1038 packets.