Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data.

Abstract: Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested information is read from memory. Additional information is read from memory based on the transaction history, wherein the requested information and the additional information are read together from memory. The requested information is cached in a segment of a cache line of the cache block and the additional information in cached another segment of the cache line. In another example, the transaction history is also updated to reflect the caching of the requested information and the additional information. In another example, read masks associated with the cache tag are referenced for the transaction history, the read masks identifying segments of a cache line previously accessed.

Abstract: A method may include transmitting, via a processor, a plurality of packets to a receiving component, such that the plurality of packets corresponds to a plurality of data operations configured to access a memory component. The plurality of packets is stored in a buffer of the receiving component upon receipt. The method may also include determining, via the processor, whether an available capacity of the buffer is less than a threshold, decreasing a transmission rate of the plurality of packets when the available capacity is less than the threshold.

Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.

Abstract: A memory device includes a memory component that stores data. The memory device also includes a processor that receives a signal indicating that the memory component is coupled to the processor and retrieves information from the memory component. The information may include one or more algorithms capable of being performed by the memory component. The processor may then receive one or more packets associated with one or more data operations regarding the memory component. The processor may then perform the one or more data operations by using the memory component to employ the one or more algorithms.

Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.

Abstract: A memory device includes a memory component that store data and a processor. The processor may generate one or more data packets associated with the memory component. Each data packet may include a transaction type field that includes data indicative of a first size of a payload of the respective data packet and a second size of an error control code in the respective data packet. Each packet may also have a payload field that includes the payload and an error control code field that includes the error control code. The processor may transmit the data packets to a requesting component, such that the requesting component identifies the payload field and the error control field of each data packet based on the data of the transaction type field in each data packet.

Abstract: A memory device includes a memory component that store data. The memory device also includes a processor that receives a signal indicating that the memory component is coupled to the processor and retrieves information from the memory component. The information may include one or more algorithms capable of being performed by the memory component. The processor may then receive one or more packets associated with one or more data operations regarding the memory component. The processor may then perform the one or more data operations by using the memory component to employ the one or more algorithms.

Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

Abstract: A memory device may include a memory component that stores data and a processor. The processor may map one or more banks or one or more virtual banks in the memory component based on one or more properties associated with the memory component and an expected random access rate for the memory component.

Abstract: A memory device includes a plurality of memory components that stores data and a processor communicatively coupled to the plurality of memory components. The processor may receive a plurality of packets associated with a plurality of data operations, such that each of the plurality of packets includes a transaction window field indicating a type of memory component associated with a respective data operation of the respective packet. The processor may also perform the plurality of data operations in a first order based on the type of memory component indicated in the transaction window field of each of the plurality of packets.

Abstract: Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested information is read from memory. Additional information is read from memory based on the transaction history, wherein the requested information and the additional information are read together from memory. The requested information is cached in a segment of a cache line of the cache block and the additional information in cached another segment of the cache line. In another example, the transaction history is also updated to reflect the caching of the requested information and the additional information. In another example, read masks associated with the cache tag are referenced for the transaction history, the read masks identifying segments of a cache line previously accessed.

Abstract: Methods are disclosed. In an embodiment of one such method, a method of receiving command signals, the method comprises receiving command signals in combination with a signal provided to a memory address node at a first clock edge and a second clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge and the second clock edge of the clock signal, represents memory commands.

Abstract: Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested information is read from memory. Additional information is read from memory based on the transaction history, wherein the requested information and the additional information are read together from memory. The requested information is cached in a segment of a cache line of the cache block and the additional information in cached another segment of the cache line. In another example, the transaction history is also updated to reflect the caching of the requested information and the additional information. In another example, read masks associated with the cache tag are referenced for the transaction history, the read masks identifying segments of a cache line previously accessed.

Abstract: A memory device includes a plurality of memory components that stores data and a processor communicatively coupled to the plurality of memory components. The processor may receive a plurality of packets associated with a plurality of data operations, such that each of the plurality of packets includes a transaction window field indicating a type of memory component associated with a respective data operation of the respective packet. The processor may also perform the plurality of data operations in a first order based on the type of memory component indicated in the transaction window field of each of the plurality of packets.

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract: A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of feature cells configured to analyze at least a portion of data to be analyzed and to selectively provide a result of the analysis. The pattern recognition processor also includes block deactivation logic configured to dynamically power-down the block.

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract: The present disclosure includes apparatuses and methods for correcting recurring errors in memory. A number of embodiments include determining whether a first subset of a group of memory cells has a recurring error associated therewith using a second subset of the group of memory cells, and responsive to a determination that the first subset of the group of memory cells has a recurring error associated therewith, correcting the recurring error using the second subset of the group of memory cells.

Abstract: A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of feature cells configured to analyze at least a portion of data to be analyzed and to selectively provide a result of the analysis. The pattern recognition processor also includes block deactivation logic configured to dynamically power-down the block.