Patents by Inventor Jacek Korec

Jacek Korec has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190245034
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Applicant: Silanna Asia Pte Ltd
    Inventors: Jacek Korec, Boyi Yang
  • Patent number: 10290703
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 14, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Jacek Korec, Boyi Yang
  • Patent number: 10290702
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) power device includes an active region formed on a bulk semiconductor substrate, the active region having a first conductivity type formed on at least a portion of the bulk semiconductor substrate. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: May 14, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Michael A. Stuber, Stuart B. Molin, Jacek Korec, Boyi Yang
  • Patent number: 9941383
    Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or grown epitaxial silicon for controlled drift region thickness and fast switching speed.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: April 10, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jacek Korec, John Manning Savidge Neilson, Sameer Pendharkar
  • Publication number: 20180069077
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Application
    Filed: November 9, 2017
    Publication date: March 8, 2018
    Applicant: Silanna Asia Pte Ltd
    Inventors: Jacek Korec, Boyi Yang
  • Patent number: 9825124
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: November 21, 2017
    Assignee: Silanna Asia Pte Ltd
    Inventors: Jacek Korec, Boyi Yang
  • Publication number: 20170229536
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) power device includes an active region formed on a bulk semiconductor substrate, the active region having a first conductivity type formed on at least a portion of the bulk semiconductor substrate. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Application
    Filed: April 21, 2017
    Publication date: August 10, 2017
    Applicant: Silanna Asia Pte Ltd
    Inventors: Michael A. Stuber, Stuart B. Molin, Jacek Korec, Boyi Yang
  • Publication number: 20160343802
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 24, 2016
    Inventors: Jacek Korec, Boyi Yang
  • Publication number: 20160276459
    Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or grown epitaxial silicon for controlled drift region thickness and fast switching speed.
    Type: Application
    Filed: May 31, 2016
    Publication date: September 22, 2016
    Inventors: Jacek Korec, John Manning Savidge Neilson, Sameer Pendharkar
  • Patent number: 9412881
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: August 9, 2016
    Assignee: Silanna Asia Pte Ltd
    Inventors: Jacek Korec, Boyi Yang
  • Patent number: 9385196
    Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or gown epitaxial silicon for controlled drift region thickness and fast switching speed.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: July 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jacek Korec, John Manning Savidge Neilson, Sameer Pendharkar
  • Patent number: 9324858
    Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: April 26, 2016
    Assignee: Vishay-Siliconix
    Inventors: Anup Bhalla, Dorman Pitzer, Jacek Korec, Xiaorong Shi, Sik Lui
  • Patent number: 9246355
    Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: January 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jacek Korec, Stephen L. Colino
  • Patent number: 9136060
    Abstract: A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be omitted and the second electrode may be in electrical contact with the substrate or may be formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor is provided by a pair of oppositely-directed diodes formed in the substrate connected in parallel with the capacitor. Capacitance is increased while maintaining a low effective series resistance. Electrodes include a plurality of fingers, which are interdigitated with the fingers of other electrode. The capacitor is fabricated in a wafer-scale process with other capacitors, where capacitors are separated from each other by a dicing technique.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: September 15, 2015
    Assignee: VISHAY-SILICONIX
    Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
  • Patent number: 8994105
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: March 31, 2015
    Assignee: Azure Silicon LLC
    Inventor: Jacek Korec
  • Patent number: 8994115
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: March 31, 2015
    Assignee: Silanna Semiconductor U.S.A., Inc.
    Inventors: Jacek Korec, Boyi Yang
  • Patent number: 8928116
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: January 6, 2015
    Assignee: Silanna Semiconductor U.S.A., Inc.
    Inventors: Jacek Korec, Boyi Yang
  • Publication number: 20140291762
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Application
    Filed: June 16, 2014
    Publication date: October 2, 2014
    Inventors: Jacek Korec, Boyi Yang
  • Patent number: 8847310
    Abstract: A MOSFET includes an active region formed on an SOI substrate. A buried well is formed in the active region. A drain region having the first conductivity type is formed in the active region and spaced laterally from a source region and the buried well. A body region is formed in the active region between the source and drain regions on the buried well, and a drift region is formed in the active region between the drain and body regions on at least a portion of the buried well. A shielding structure is formed proximate the upper surface of the active region, overlapping a gate. During conduction, the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes the drift region. The MOSFET is configured to sustain a linear mode of operation of an inversion channel formed under the gate.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: September 30, 2014
    Assignee: Azure Silicon LLC
    Inventor: Jacek Korec
  • Publication number: 20140284701
    Abstract: A MOSFET includes an active region formed on an SOI substrate. A buried well is formed in the active region. A drain region having the first conductivity type is formed in the active region and spaced laterally from a source region and the buried well. A body region is formed in the active region between the source and drain regions on the buried well, and a drift region is formed in the active region between the drain and body regions on at least a portion of the buried well. A shielding structure is formed proximate the upper surface of the active region, overlapping a gate. During conduction, the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes the drift region. The MOSFET is configured to sustain a linear mode of operation of an inversion channel formed under the gate.
    Type: Application
    Filed: June 3, 2014
    Publication date: September 25, 2014
    Applicant: Azure Silicon LLC
    Inventor: Jacek Korec