Abstract: A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus.

Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: A trench-gated power MOSFET contains a highly doped region in the body region which forms a PN junction diode with the drain at the center of the MOSFET cell. This diode has an avalanche breakdown voltage which is lower than the breakdown voltage of the drain-body junction near to the wall of the trench. Thus the MOSFET breaks down in the center of the cell avoiding the generation of hot carriers that could damage the gate oxide layer. The drain-body junction is located at a level which is above the bottom of the trench, thereby avoiding any deep diffusion that would increase the cell width and reduce the cell packing density. This compact structure is achieved by limiting the thermal budget to which the device is exposed after the body region is implanted. As a result, the body and its highly doped region do not diffuse significantly, and dopant from the highly doped region does not get into the channel region of the device so as to increase its threshold voltage.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: A Schottky recitfier includes a semiconductor body and a rectifying interface between the semiconductor body and a metal layer. A plurality of trenches are formed in the surface of the semiconductor body, the trenches being separated by mesas, and regions of a conductivity type opposite to the conductivity type of the body is formed along the sidewalls and bottoms of the trenches, the regions forming PN junctions with the rest of the mesas. When the rectifier is reverse-biased, the depletion regions along the PN junctions merge to occupy the entire width of the mesas, thereby protecting the rectifying interface from barrier lowering and resulting current leakage. The use of trenches allows a high aspect ratio, i.e., the ratio of the length to the width of the current “channels” in the mesas (the length being equal to the depth of the trenches), thereby maximizing the area available for current flow and reducing the resistance of the rectifying device in the forward direction.

Abstract: In a semiconductor package for a chip having terminals on both sides, for example, a power MOSFET in which the gate and source terminals are on the front side and the drain terminal is on the back side, electrical contact is made with the back side terminal by extending vias, which can take the form of trenches, holes or other cavities, either entirely or patrially through the chip. The vias are filled with a metal or other electrically conductive material. The process is performed on the chips in a wafer simultaneously. The resulting package is compact and economical to manufacture and can readily be mounted, flip-chip style, on a printed circuit board.

Abstract: A trench-gated power MOSFET contains a highly doped region in the body region which forms a PN junction diode with the drain at the center of the MOSFET cell. This diode has an avalanche breakdown voltage which is lower than the breakdown voltage of the drain-body junction near to the wall of the trench. Thus the MOSFET breaks down in the center of the cell avoiding the generation of hot carriers that could damage the gate oxide layer. The drain-body junction is located at a level which is above the bottom of the trench, thereby avoiding any deep diffusion that would increase the cell width and reduce the cell packing density. This compact structure is achieved by limiting the thermal budget to which the device is exposed after the body region is implanted. As a result, the body and its highly doped region do not diffuse significantly, and dopant from the highly doped region does not get into the channel region of the device so as to increase its threshold voltage.

Abstract: A trench-gated power MOSFET contains a highly doped region in the body region which forms a PN junction diode with the drain at the center of the MOSFET cell. This diode has an avalanche breakdown voltage which is lower than the breakdown voltage of the drain-body junction near to the wall of the trench. Thus the MOSFET breaks down in the center of the cell avoiding the generation of hot carriers that could damage the gate oxide layer. The drain-body junction is located at a level which is above the bottom of the trench, thereby avoiding any deep diffusion that would increase the cell width and reduce the cell packing density. This compact structure is achieved by limiting the thermal budget to which the device is exposed after the body region is implanted. As a result, the body and its highly doped region do not diffuse significantly, and dopant from the highly doped region does not get into the channel region of the device so as to increase its threshold voltage.

Abstract: In a trench-gated MOSFET, a lightly doped drift region of the N-type drain lies in the mesa between the trenches. The gate is doped with N-type material so that depletion regions are formed in the drift region when the gate voltage is equal to zero. The depletion regions merge at the center of the mesa, pinching off the flow of current when the device is turned off. This current-pinching effect allows the P-type body region to be made shallower and doped more lightly than usual without creating a punchthrough problem, because the barrier represented by the depletion regions adds to the normal current blocking capability of the PN junction between the body and drain regions. When the device is turned on by biasing the gate to a positive voltage, a low resistance accumulation layer forms in the drift region adjacent the trenches.

Abstract: In an emitter-switched thyristor with a main thyristor (TH) composed of a p+ anode emitter (1), a drift zone (3') of opposite conductivity type, a zone (4) which has in the switched-off state a blocking zone with respect to zone (3) and an emitter zone (5) at the cathode side, again with an opposite conductivity type, so that a p+n-pn+ zone sequence results, a transistor structure (T) composed of the first three zones of alternating conductivity is provided in parallel thereto with an emitter (1), base (3) and a collector (8). This structure contains a NMOSFET (M1) for directly driving the cathode emitters (5) through the cathode connection (KA). The source of this transistor is contacted by the cathode, as well as the collector zone (8) which forms the channel zone of the MOSFET at the surface of the semiconductor. The corresponding drain zone is connected to the n+ cathode emitter (5) of the main thyristor (TH) by an electric conductor (6).

Abstract: A trench-gated Schottky diode of the kind described in U.S. Pat. No. 5,365,102 is provided with an integral clamping diode which protects the gate oxide from damage from high electric fields and hot carrier generation when the device is reverse-biased. The clamping diode is arranged in parallel with the normal current path through the Schottky diode and comprises a PN junction created by a diffusion of opposite conductivity to the semiconductor material of the Schottky diode. In a preferred embodiment, the clamping diode is selected to prevent significant impact ionization near the trenched gate during either steady state- or deep depletion-induced avalanche breakdown.

Abstract: The gate of a MOSFET is located in a lattice of trenches which define a plurality of cells. Most of the cells contain a MOSFET, but a selected number of the cells at predetermined locations in the lattice contain either a PN diode or a Schottky diode. The PN and Schottky diodes are connected in parallel with the channels in the MOSFET cells, with their anodes tied to the anode of the parasitic diodes in the MOSFET cells and their cathodes tied to the cathode of the parasitic diodes. When the MOSFET is biased in the normal direction (with the parasitic diode reverse-biased), the PN diodes provide a predictable breakdown voltage for the device and ensure that avalanche breakdown occurs at a location away from the trench gate where the hot carriers generated by the breakdown cannot damage the oxide layer which lines the walls of the trench. When the device is biased in the opposite direction, the Schottky diodes conduct and thereby limit charge storage at the PN junctions in the diode and MOSFET cells.

Abstract: The invention concerns a semiconductor component which can be controlled on the anode side and whose semiconductor body comprises a plurality of adjacent, parallel-connected unit cells having a thyristor structure. A lightly doped n-base region (3) is adjoined on both sides by highly doped p-regions constituting p-base region (2) and p-emitter region (4). The p-base region (2) is followed by a highly doped n-emitter (1) which contacts a cathode electrode (7). Integrated in the p-emitter region (4) is a first n-channel MOSFET (M1) which is connected in series with the thyristor structure by means of a floating electrode (FE). The drain electrode (5b) of the first MOSFET (M1) is provided with an outer anode (8) which has no contact with the p-emitter region (4). A second n-channel MOSFET (M2) is integrated between the n-base region (3) and the drain region (5b) of the first MOSFET (M1).

Abstract: SiC field-effect transistors with source, gate and drain contacts and in which the source contacts are located on the surface of the semiconductor wafer, the drain contacts on the underside of the wafer and the gate contacts in trench-like structures. The trench-like structures surround the source electrodes of the transistors in the shape of a ring and the gate contacts are connected to each other on the floors of the trenches.

Abstract: The invention concerns a field-effect controlled semiconductor component with at least four regions of alternating opposite performance types: an anode-side emitter region, a first and a second base region connected to the emitter region, and a cathode-side emitter region; the cathode-side emitter region and the first base region from the source and drain of an MOS field effect transistor. The component also comprises an anode contact, a contact at the cathode-side emitter region and a control electrode contact of the MOS field effect transistor. The invention lies in the fact that a p+ region (36) which is adjacent to the cathode-side base region, separate, and accomodated in the anode-side n- base region (20), is connected via a separate component as a coupling element (80) with non-linear current/voltage characteristics to the cathode contact, the said region (36) being directly surrounded by the anode-side base region (20).

Abstract: A field-effect-controlled semiconductor device has a cathode, an anode, and a gate, and extends laterally on a first insulating layer covering a substrate. The device includes a main thyristor, a MOSFET switch and a diode which connects a highly doped region embedded in a first part of a second base region of the thyristor to the cathode of the device.