Abstract: Treatment of aneurysmal blood vessels with local delivery of therapeutic agents thereby reduces or lessens the severity of an aneurysm, and, where used in conjunction with the placement of an excluding device, provides for more rapid recovery of the blood vessel from any disturbance occurring during placement of the excluding device. Therapeutic agents are placed in the aneurysmal site in a time-release carrier medium, such that the therapeutic agent is released into the aneurysmal site over a period of time without the need to provide systemic introduction of the therapeutic agent. The carrier may be introduced through the patient's dermis, such as with the use of a laparoscope, or intravacularly, through the use of a catheter. The carrier may be in a solid matrix, viscous liquid or liquid form.

Abstract: The present invention encompasses methods and apparatus for minimizing the risks inherent in endovascular grafting for blood vessel therapy and repair. The invention involves delivering adult stem cells, embryonic stem cells, progenitor cells, fibroblasts, or smooth muscle cells to the diseased blood vessel.

Abstract: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

Abstract: A method and device for the treatment of an aneurysm are provided. Different therapeutic agents are delivered to the aneurysmal site by a reservoir and delivery means in a localized, and, in some embodiments, time-released regimen, to treat, limit and reduce the severity of the aneurysm.

Abstract: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

Abstract: A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

Abstract: A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

Abstract: A method of using a delivery system includes advancing a stent to be located within an ostium of a vessel; advancing a basket actuation button of a handle to deploy a basket of the basket assembly; moving the basket into engagement with a parent vessel, the basket having a larger diameter than a diameter of the ostium; deploying the stent within an ostial lesion of the vessel; and contracting the basket.

Abstract: An endoluminal stent graft includes a healing-promoting material to enhance the “healing” of the proximal and/or distal neck(s) of the endoluminal stent graft and the vessel wall; the risk of migration and the occurrence of Type 1 endoleaks is reduced. The healing-promoting material is located within a proximal anchor region located near the proximal neck opening of the endoluminal stent graft and optionally within one or more distal anchor regions located near one or more distal neck openings of the endoluminal stent graft.

Abstract: Methods of treating an aneurysm in a patient in need thereof are provided. The methods comprise delivering to a treatment site an effective amount of a fatty acid inhibitor of a matrix metalloproteinase (MMP) such that the fatty acid inhibitor of the MMP causes the regression of a pre-existing aneurysm. Additionally, an implantable medical device is provided for implanting in a vessel wall of a patient comprising a structural support and a fatty acid inhibitor of an MMP.

Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.

Abstract: A method of securing a prosthesis placed at a desired site in a passageway of a human body comprises delivering a fastener having a proximal piercing end portion and a distal piercing end portion to a site where a prosthesis having a tubular wall has been placed in the passageway, which has a wall, advancing the proximal piercing end portion beyond the prosthesis, penetrating the proximal piercing end portion into the wall of the passageway without passing the proximal piercing end portion through the tubular wall of the prosthesis, and passing the distal piercing end portion through the tubular wall of the prosthesis and into the wall of the passageway. One surgical fastener delivery apparatus for delivering a surgical fastener to a target site comprises a support having a first end, a second end, and a longitudinal axis and being adapted for placement in a passageway in a human body.

Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

Abstract: The invention provides a method of providing an endovascular bypass. The method includes the steps of inserting an elastic needle carrying a guidewire adjacent an ostium via a catheter and extending the needle through a branch vessel wall. The method continues by extending the needle through the extravascular space and inserting the needle through a main vessel wall to create an opening. The needle is retracted, leaving the guidewire in place. A bypass stent graft is inserted along the guidewire to provide a pathway between the branch vessel and the main vessel, and the inserted bypass stent graft is expanded. The branch vessel is occluded between the ostium of the bypass stent graft and the main vessel, and a main stent graft is inserted in the main vessel proximate the opening in the main vessel wall.

Abstract: Methods for ameliorating stent graft migration and endoleak using treatment site-specific cell growth promoting compositions in combination with stent grafts are disclosed. Also disclosed are application of cell growth promoting compositions such as, but not limited to, autologous platelet gel compositions directly to treatment sites during or after stent graft implantation.

Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

Abstract: A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable.

Abstract: A low powered activation electronic device includes a power source, an electronic circuit, having two spaced apart electrodes, electrically connected to the power source to form an opened circuit, and two fabric contacts made of textile material provided at the two electrodes of the electronic circuit, wherein the electronic circuit is formed a closed circuit to activate the electronic device in responsive to a physical touch by a human operator at the two fabric contacts.

Abstract: A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.