Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.

Abstract: Devices and methods for improvement of functioning of a valve of a subject are disclosed. A device exhibiting an outward bias at its proximal end and an outward bias at its distal end, disposed at an angle to the bias at the proximal end is described. A device having a first arm and a second arm separated by a peak and having shoulders is also described. Alternative embodiments which function to decrease the distance between valve leaflets, having a first arm and a second arm biased toward one another are also disclosed. Several embodiments which may have mirror image ends are also disclosed. Any of the devices may have barbs, umbrella structures, sutures, or a variety of spring elements. Devices may be implanted surgically, percutaneously or subcutaneously. Methods and devices for delivery and deployment of devices are disclosed as well as methods for treatment of a valve of a subject.

Abstract: An excluding device is inserted in a vessel. An excluded space is formed between a portion of a wall of the vessel and a portion of an exterior surface of the excluding device. A treatment element is passed through a channel of the excluding device into the excluded space. The channel is sealed using a cuff or patch after the passing of the treatment element(s) such as fill material or drugs and drug releasing elements.

Abstract: The present invention relates to methods and devices to contribute to the treatment of aneurysms. More specifically, the present invention relates to methods and devices to contribute to contribute to the treatment of aneurysms by delivering bioactive agents via various delivery devices of collagen III and/or collagen III and thrombin.

Abstract: A polymer coating/ring is employed to aid in the sealing and connection of modular elements used in body flow lumens for the exclusion and bypass of diseased regions of the flow lumen, such as where aneurysm occurs adjacent to branching blood vessels.

Abstract: A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects. The MODFET design includes a high-mobility conducting channel layer wherein the method allows the counter doping to be formed using a standard technique such as ion implantation, and further allows the high-mobility channel to be in close proximity to the counter doping without degradation of the mobility.

Abstract: A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 OE from the first layer of greater than 1×1019 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET's, and HBT's.

Abstract: Methods and devices for improving biofixation of implantable vascular devices are provided. The methods and devices improve biofixation of implantable vascular devices by providing one or more thrombus-eliminating agents at a treatment site before and/or during and/or after vascular device implantation.

Abstract: Methods and devices for ameliorating stent graft migration and endoleak using treatment site-specific cell growth promoting compositions in combination with stent grafts are disclosed. Also disclosed is coating of autologous growth factor compositions onto stent grafts prior to stent graft implantation. Additional embodiments include stent grafts having autologous growth factor composition coatings useful for treating aneurysms.

Abstract: Method and devices to administer a bioactive material within a vessel while maintaining nearly-constant pressure within the vessel are disclosed. In one embodiment the methods and devices include a multi-lumen catheter to administer bioactive materials and simultaneously drain or evacuate excess fluid or bio-inactive materials at an aneurysm site within a vessel.

Abstract: Methods for ameliorating stent graft migration and endoleak using treatment site-specific cell growth promoting compositions in combination with stent grafts are disclosed. Also disclosed are application of cell growth promoting compositions such as, but not limited to, autologous platelet gel compositions directly to treatment sites before, during or after stent graft implantation. Additional embodiments include medical devices having autologous platelet gel coatings and/or autologous platelet gel delivery devices useful for treating aneurysms.

Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.

Abstract: A low powered activation electronic device includes a power source, an electronic circuit, having two spaced apart electrodes, electrically connected to the power source to form an opened circuit, and two fabric contacts made of textile material provided at the two electrodes of the electronic circuit, wherein the electronic circuit is formed a closed circuit to activate the electronic device in responsive to a physical touch by a human operator at the two fabric contacts.

Abstract: A method and apparatus for a securement device useful for the treatment of aneurysms includes a hub and, in one aspect, a plurality of arms or spikes in a star pattern extendable therefrom and into engagement with a blood vessel wall. The securement device may be deployed to anchor a secondary device, such as an exclusion device for example a stent graft, in position in a flow lumen and thereby prevent the migration of the exclusion device in the flow lumen. The arms may be positioned to penetrate through the exclusion device and thence into the flow lumen wall to provide such securement.

Abstract: A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate comprising a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

Abstract: The invention provides a method of providing an endovascular bypass. The method includes the steps of inserting an elastic needle carrying a guidewire adjacent an ostium via a catheter and extending the needle through a branch vessel wall. The method continues by extending the needle through the extravascular space and inserting the needle through a main vessel wall to create an opening. The needle is retracted, leaving the guidewire in place. A bypass stent graft is inserted along the guidewire to provide a pathway between the branch vessel and the main vessel, and the inserted bypass stent graft is expanded. The branch vessel is occluded between the ostium of the bypass stent graft and the main vessel, and a main stent graft is inserted in the main vessel proximate the opening in the main vessel wall.

Abstract: Methods and apparatus for minimizing the risks inherent in endovascular grafting for aneurysm repair are provided, including the implantation and time-controlled release of at least one bioactive agent at the aneurysmal site.

Abstract: A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.