Patents by Inventor Jack Kavalieros

Jack Kavalieros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer
    Publication number: 20070045753
    Abstract: A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 ? to 60 ?. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 1, 2007
    Inventors: Sangwoo Pae, Jose Maiz, Justin Brask, Gilbert Dewey, Jack Kavalieros, Robert Chau, Suman Datta
  • Method for making a semiconductor device that includes a metal gate electrode
    Patent number: 7183184
    Abstract: A method for making a semiconductor device is described. That method comprises forming a hard mask and an etch stop layer on a patterned sacrificial gate electrode layer. After first and second spacers are formed on opposite sides of that patterned sacrificial layer, the patterned sacrificial layer is removed to generate a trench that is positioned between the first and second spacers. At least part of the trench is filled with a metal layer.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Uday Shah, Chris E. Barns, Robert S. Chau
  • Reducing gate dielectric material to form a metal gate electrode extension
    Publication number: 20070040227
    Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have vertical portions that may be exposed to a reduction reaction. As a result of the reduction reaction, the vertical portions may be converted to metal, which adds to the existing gate electrode. In some cases, removing the vertical dielectric portions reduces fringe capacitance and may also advantageously slightly increased underdiffusion without adding heat, in some embodiments.
    Type: Application
    Filed: October 26, 2006
    Publication date: February 22, 2007
    Inventors: Suman Datta, Justin Brask, Jack Kavalieros, Mark Doczy, Matthew Metz, Robert Chau
  • Lateral undercut of metal gate in SOI device
    Publication number: 20070040223
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.
    Type: Application
    Filed: August 17, 2005
    Publication date: February 22, 2007
    Inventors: Suman Datta, Justin Brask, Jack Kavalieros, Brian Doyle, Gilbert Dewey, Mark Doczy, Robert Chau
  • Planarizing a semiconductor structure to form replacement metal gates
    Publication number: 20070037372
    Abstract: A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop.
    Type: Application
    Filed: October 13, 2006
    Publication date: February 15, 2007
    Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Uday Shah, Chris Barns, Matthew Metz, Suman Datta, Robert Chau
  • Tri-gate devices and methods of fabrication
    Publication number: 20070034972
    Abstract: The present invention is a semiconductor device comprising a carbon nanotube body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the carbon nanotube body and on the laterally opposite sidewalls of the carbon nanotube body. A gate electrode is formed on the gate dielectric on the top surface of the carbon nanotube body and adjacent to the gate dielectric on the laterally opposite sidewalls of the carbon nanotube body.
    Type: Application
    Filed: October 25, 2006
    Publication date: February 15, 2007
    Inventors: Robert Chau, Brian Doyle, Jack Kavalieros, Douglas Barlage, Suman Datta
  • Method for making a semiconductor device that includes a metal gate electrode
    Patent number: 7176090
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Brian S. Doyle, Robert S. Chau
  • Reducing the dielectric constant of a portion of a gate dielectric
    Publication number: 20070029627
    Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.
    Type: Application
    Filed: October 10, 2006
    Publication date: February 8, 2007
    Inventors: Suman Datta, Jack Kavalieros, Mark Doczy, Matthew Metz, Justin Brask, Robert Chau
  • Carbon nanotube energy well (CNEW) field effect transistor
    Patent number: 7170120
    Abstract: A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: January 30, 2007
    Assignee: Intel Corporation
    Inventors: Suman Datta, Marko Radosavljevic, Brian Doyle, Jack Kavalieros, Justin Brask, Amlan Majumdar, Robert S. Chau
  • Method for making a semiconductor device that includes a metal gate electrode
    Patent number: 7160767
    Abstract: A method for making a semiconductor device is described. That method comprises forming a dummy dielectric layer that is at least about 10 angstroms thick on a substrate, and forming a sacrificial layer on the dummy dielectric layer. After removing the sacrificial layer and the dummy dielectric layer to generate a trench that is positioned between first and second spacers, a gate dielectric layer is formed on the substrate at the bottom of the trench, and a metal layer is formed on the gate dielectric layer.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: January 9, 2007
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Uday Shah, Mark L. Doczy, Matthew V. Metz, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Patent number: 7160779
    Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer that contacts a metal oxide layer. The metal oxide layer is generated by forming a metal layer, then oxidizing the metal layer.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: January 9, 2007
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Jack Kavalieros, Justin K. Brask, Matthew V. Metz, Suman Datta, Brian S. Doyle, Robert S. Chau
  • Block contact architectures for nanoscale channel transistors
    Publication number: 20070001219
    Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Marko Radosavljevic, Amlan Majumdar, Brian Doyle, Jack Kavalieros, Mark Doczy, Justin Brask, Uday Shah, Suman Datta, Robert Chau
  • Semiconductor device structures and methods of forming semiconductor structures
    Publication number: 20070001173
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Application
    Filed: June 21, 2005
    Publication date: January 4, 2007
    Inventors: Justin Brask, Jack Kavalieros, Uday Shah, Suman Datta, Amlan Majumdar, Robert Chau, Brian Doyle
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Patent number: 7157378
    Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Chris E. Barns, Mark L. Doczy, Uday Shah, Jack Kavalieros, Matthew V. Metz, Suman Datta, Anne E. Miller, Robert S. Chau
  • Strained field effect transistors
    Publication number: 20060292776
    Abstract: An NMOS transistor may be formed with a biaxially strained silicon upper layer having a thickness of greater than 500 Angstroms. The resulting NMOS transistor may have good performance and may exhibit reduced self-heating. A PMOS transistor may be formed with both a biaxially and uniaxially strained silicon germanium layer. A source substrate bias applied to both NMOS and PMOS transistors can enhance their performance.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventors: Been-Yih Jin, Robert Chau, Suman Datta, Brian Doyle, Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz, Markus Kuhn, Marko Radosavlievic, M. Shaheed, Patrick Keys
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Patent number: 7153784
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Uday Shah, Chris E. Barns, Matthew V. Metz, Suman Datta, Annalisa Cappellani, Robert S. Chau
  • CMOS device with metal and silicide gate electrodes and a method for making it
    Patent number: 7153734
    Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
    Publication number: 20060286729
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the-removal of a nitride etch stop layer.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 21, 2006
    Inventors: Jack Kavalieros, Annalisa Cappellani, Justin Brask, Mark Doczy, Matthew Metz, Suman Datta, Chris Barns, Robert Chau
  • Metal gate device with reduced oxidation of a high-k gate dielectric
    Publication number: 20060284271
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 21, 2006
    Inventors: Brian Doyle, Jack Kavalieros, Justin Brask, Matthew Mertz, Mark Doczy, Suman Datta, Robert Chau
  • Method for fabricating transistor with thinned channel
    Publication number: 20060286755
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Inventors: Justin Brask, Robert Chau, Suman Datta, Mark Doczy, Brian Doyle, Jack Kavalieros, Amlan Majumdar, Matthew Metz, Marko Radosavljevic