Patents by Inventor Jack Kavalieros

Jack Kavalieros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating transistor with thinned channel
    Publication number: 20060286755
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Inventors: Justin Brask, Robert Chau, Suman Datta, Mark Doczy, Brian Doyle, Jack Kavalieros, Amlan Majumdar, Matthew Metz, Marko Radosavljevic
  • Semiconductor device with a high-k gate dielectric and a metal gate electrode
    Publication number: 20060278941
    Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.
    Type: Application
    Filed: June 13, 2005
    Publication date: December 14, 2006
    Inventors: Matthew Metz, Suman Datta, Mark Doczy, Justin Brask, Jack Kavalieros, Robert Chau
  • Method and apparatus for improving stability of a 6T CMOS SRAM cell
    Publication number: 20060281236
    Abstract: The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.
    Type: Application
    Filed: August 21, 2006
    Publication date: December 14, 2006
    Inventors: Suman Datta, Brian Doyle, Robert Chau, Jack Kavalieros, Bo Zheng, Scott Hareland
  • Semiconductor device with a high-k gate dielectric and a metal gate electrode
    Patent number: 7148548
    Abstract: A semiconductor device is described that comprises a gate dielectric and a metal gate electrode that comprises an aluminide.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: December 12, 2006
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Justin K. Brask, Suman Datta, Robert S. Chau
  • Reducing the dielectric constant of a portion of a gate dielectric
    Patent number: 7148099
    Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: December 12, 2006
    Assignee: Intel Corporation
    Inventors: Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau
  • Reducing gate dielectric material to form a metal gate electrode extension
    Patent number: 7144783
    Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have vertical portions that may be exposed to a reduction reaction. As a result of the reduction reaction, the vertical portions may be converted to metal, which adds to the existing gate electrode. In some cases, removing the vertical dielectric portions reduces fringe capacitance and may also advantageously slightly increased underdiffusion without adding heat, in some embodiments.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: December 5, 2006
    Assignee: Intel Corporation
    Inventors: Suman Datta, Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew Metz, Robert S. Chau
  • Planarizing a semiconductor structure to form replacement metal gates
    Patent number: 7138323
    Abstract: A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: November 21, 2006
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Uday Shah, Chris E. Barns, Matthew V. Metz, Suman Datta, Robert S. Chau
  • Method and apparatus for improving stability of a 6T CMOS SRAM cell
    Patent number: 7138305
    Abstract: The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: November 21, 2006
    Assignee: Intel Corporation
    Inventors: Suman Datta, Brian S. Doyle, Robert S. Chau, Jack Kavalieros, Bo Zheng, Scott A. Hareland
  • Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions
    Publication number: 20060258072
    Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further comprises a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.
    Type: Application
    Filed: May 13, 2005
    Publication date: November 16, 2006
    Inventors: Jack Kavalieros, Matthew Metz, Gilbert Dewey, Been-Yih Jin, Justin Brask, Suman Datta, Robert Chau
  • Method for etching a thin metal layer
    Patent number: 7129182
    Abstract: A method for etching a metal layer is described. That method comprises forming a metal layer on a substrate, then exposing part of the metal layer to a wet etch chemistry that comprises an active ingredient with a diameter that exceeds the thickness of the metal layer.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Uday Shah, Matthew V. Metz, Robert S. Chau, Robert B. Turkot, Jr.
  • Compensating for induced strain in the channels of metal gate transistors
    Publication number: 20060237801
    Abstract: Strained channel field effect transistors may have a threshold voltage shift. This threshold voltage shift may be compensated for by adjusting channel doping. But this also adversely affects mobility. The threshold voltage shift may be compensated, without adversely affecting mobility, by tailoring the workfunction of a metal gate electrode used in the transistor to adequately compensate for that threshold voltage shift. For example, in some embodiments, an appropriate metal may be selected with a slightly higher workfunction or, in other cases, the workfunction of a selected metal may be adjusted by, for example, doping the metal gate electrode with a material which increases the workfunction of the gate electrode.
    Type: Application
    Filed: April 20, 2005
    Publication date: October 26, 2006
    Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz, Suman Datta, Brian Doyle, Robert Chau
  • Compensating the workfunction of a metal gate transistor for abstraction by the gate dielectric layer
    Patent number: 7125762
    Abstract: A metal gate transistor may include a metal layer over a high dielectric constant dielectric layer. The dielectric layer abstracts electronegativity from said metal layer, altering its workfunction. The workfunction of the metal layer may be set to compensate for the dielectric layer abstraction.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
  • Multilayer metal gate electrode
    Patent number: 7126199
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer and a cap metal layer is formed over the workfunction setting metal layer.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Chris Barns, Matthew V. Metz, Suman Datta, Robert S. Chau
  • Tri-gate devices and methods of fabrication
    Publication number: 20060228840
    Abstract: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.
    Type: Application
    Filed: December 7, 2005
    Publication date: October 12, 2006
    Inventors: Robert Chau, Brian Doyle, Jack Kavalieros, Douglas Barlage, Suman Datta, Scott Hareland
  • Semiconductor device with a high-k gate dielectric and a metal gate electrode
    Publication number: 20060220090
    Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed over a channel that is positioned within a substrate, and a metal gate electrode that is formed on the high-k gate dielectric layer. The high-k gate dielectric layer has off-state leakage characteristics that are superior to those of a silicon dioxide based gate dielectric, and on-state mobility characteristics that are superior to those of a high-k gate dielectric that comprises an isotropic material.
    Type: Application
    Filed: March 23, 2005
    Publication date: October 5, 2006
    Inventors: Matthew Metz, Suman Datta, Mark Doczy, Jack Kavalieros, Justin Brask, Brian Doyle, Marko Radosavljevic, Robert Chau
  • CARBON NANOTUBE ENERGY WELL (CNEW) FIELD EFFECT TRANSISTOR
    Publication number: 20060220074
    Abstract: A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Inventors: Suman Datta, Marko Radosavljevic, Brian Doyle, Jack Kavalieros, Justin Brask, Amlan Majumdar, Robert Chau
  • Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit
    Publication number: 20060214237
    Abstract: Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a replacement process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.
    Type: Application
    Filed: May 5, 2006
    Publication date: September 28, 2006
    Inventors: Matthew Metz, Suman Datta, Jack Kavalieros, Mark Doczy, Justin Brask, Robert Chau
  • Field effect transistor with metal source/drain regions
    Publication number: 20060202266
    Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 14, 2006
    Inventors: Marko Radosavljevic, Suman Datta, Brian Doyle, Jack Kavalieros, Justin Brask, Mark Doczy, Amian Majumdar, Robert Chau
  • Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
    Publication number: 20060205167
    Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.
    Type: Application
    Filed: March 11, 2005
    Publication date: September 14, 2006
    Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz, Suman Datta, Brian Doyle, Robert Chau, Everett Wang, Philippe Matagne, Lucian Shifren, Been Jin, Mark Stettler, Martin Giles
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Publication number: 20060186484
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: February 23, 2005
    Publication date: August 24, 2006
    Inventors: Robert Chau, Suman Datta, Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz