Patents by Inventor Jack Kavalieros

Jack Kavalieros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for making a semiconductor device having a high-k gate dielectric
    Patent number: 7442983
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: October 28, 2008
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin K. Brask, Jack Kavalieros, Matthew V. Metz, Adrian B. Sherrill, Markus Kuhn, Robert S. Chau
  • Block Contact Architectures for Nanoscale Channel Transistors
    Publication number: 20080258207
    Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.
    Type: Application
    Filed: September 14, 2007
    Publication date: October 23, 2008
    Inventors: Marko Radosavljevic, Amlan Majumdar, Brian S. Doyle, Jack Kavalieros, Mark L. Doczy, Justin K. Brask, Uday Shah, Suman Datta, Robert S. Chau
  • Method for fabricating metal gate structures
    Patent number: 7439571
    Abstract: Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: October 21, 2008
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Mark Y. Liu, Jack Kavalieros, Justin K. Brask, Matthew V. Metz, Robert S. Chau
  • Forming dual metal complementary metal oxide semiconductor integrated circuits
    Patent number: 7439113
    Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: October 21, 2008
    Assignee: Intel Corporation
    Inventors: Mark Doczy, Mitchell Taylor, Justin K. Brask, Jack Kavalieros, Suman Datta, Matthew V. Metz, Robert S. Chau, Jack Hwang
  • High quality silicon oxynitride transition layer for high-k/metal gate transistors
    Publication number: 20080242012
    Abstract: A method for fabricating a high quality silicon oxynitride layer for a high-k/metal gate transistor comprises depositing a high-k dielectric layer on a substrate, depositing a barrier layer on the high-k dielectric layer, wherein the barrier layer includes at least one of nitrogen or oxygen, depositing a capping layer on the barrier layer, and annealing the substrate at a temperature that causes at least a portion of the nitrogen and/or oxygen in the barrier layer to diffuse to an interface between the high-k dielectric layer and the substrate. The diffused nitrogen or oxygen forms a high-quality silicon oxynitride layer at the interface. The high-k dielectric layer, the barrier layer, and the capping layer may then be etched to form a gate stack for use in a high-k/metal gate transistor. The capping layer may be replaced with a metal gate electrode using a replacement metal gate process.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Inventors: Sangwoo Pae, Jose Maiz, Gilbert Dewey, Matthew V. Metz, Markus Kuhn, Mark Doczy, Jack Kavalieros
  • Tri-gate devices and methods of fabrication
    Patent number: 7427794
    Abstract: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: September 23, 2008
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Brian S. Doyle, Jack Kavalieros, Douglas Barlage, Suman Datta, Scott A. Hareland
  • Carbon nanotube energy well (CNEW) field effect transistor
    Patent number: 7427541
    Abstract: A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: September 23, 2008
    Assignee: Intel Corporation
    Inventors: Suman Datta, Marko Radosavljevic, Brian Doyle, Jack Kavalieros, Justin Brask, Amlan Majumdar, Robert S. Chau
  • Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics
    Patent number: 7425490
    Abstract: In a metal gate replacement process, a gate electrode stack may be formed of a dielectric covered by a sacrificial metal layer covered by a polysilicon gate electrode. In subsequent processing of the source/drains, high temperature steps may be utilized. The sacrificial metal layer prevents reactions between the polysilicon gate electrode and the underlying high dielectric constant dielectric. As a result, adverse consequences of the reaction between the polysilicon and the high dielectric constant dielectric material can be reduced.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: September 16, 2008
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Uday Shah, Matthew Metz, Suman Datta, Robert S. Chau
  • Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
    Patent number: 7422971
    Abstract: The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Brian Doyle, Jack Kavalieros, Robert Chau
  • Facilitating removal of sacrificial layers via implantation to form replacement metal gates
    Patent number: 7422936
    Abstract: Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. A hard mask may also be applied over the gate structure and implanted so that the hard mask may be more readily removed.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Chris E. Barns, Matt Prince, Mark L. Doczy, Justin K. Brask, Jack Kavalieros
  • Reducing oxidation under a high K gate dielectric
    Publication number: 20080211033
    Abstract: A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier.
    Type: Application
    Filed: May 7, 2008
    Publication date: September 4, 2008
    Inventors: Robert B. Turkot, Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Uday Shah, Suman Datta, Robert S. Chau
  • Lateral undercut of metal gate in SOI device
    Publication number: 20080188041
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.
    Type: Application
    Filed: March 26, 2008
    Publication date: August 7, 2008
    Inventors: Suman Datta, Justin K. Brask, Jack Kavalieros, Brian S. Doyle, Gilbert Dewey, Mark L. Doczy, Robert S. Chau
  • Lateral undercut of metal gate in SOI device
    Patent number: 7402875
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: July 22, 2008
    Assignee: Intel Corporation
    Inventors: Suman Datta, Justin K. Brask, Jack Kavalieros, Brian S. Doyle, Gilbert Dewey, Mark L. Doczy, Robert S. Chau
  • Method of combining floating body cell and logic transistors
    Publication number: 20080157162
    Abstract: An integrated circuit having both floating body cells and logic devices fabricated in a bulk silicon substrate is described. The floating body cells have electrically floating bodies formed by oxidizing a lower portion of the cell bodies to electrically isolate them from the substrate.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: Brian S. Doyle, Suman Datta, Jack Kavalieros, Robert Chau
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Patent number: 7390709
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: June 24, 2008
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Uday Shah, Matthew V. Metz, Suman Datta, Ramune Nagisetty, Robert S. Chau
  • Forming field effect transistors from conductors
    Patent number: 7390947
    Abstract: A nanotube transistor, such as a carbon nanotube transistor, may be formed with a top gate electrode and a spaced source and drain. Conduction along the transistor from source to drain is controlled by the gate electrode. Underlying the gate electrode are at least two nanotubes. In some embodiments, the substrate may act as a back gate.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: June 24, 2008
    Assignee: Intel Corporation
    Inventors: Amlan Majumdar, Justin K. Brask, Marko Radosavljevic, Suman Datta, Brian S. Doyle, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Robert S. Chau, Uday Shah, James Blackwell
  • Reducing oxidation under a high K gate dielectric
    Patent number: 7387927
    Abstract: A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: June 17, 2008
    Assignee: Intel Corporation
    Inventors: Robert B. Turkot, Jr., Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Uday Shah, Suman Datta, Robert S. Chau
  • METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A HIGH-K DIELECTRIC LAYER AND A METAL GATE ELECTRODE
    Publication number: 20080135952
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.
    Type: Application
    Filed: February 14, 2008
    Publication date: June 12, 2008
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Uday Shah, Chris E. Barns, Matthew V. Metz, Suman Datta, Annalisa Cappellani, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Patent number: 7384880
    Abstract: A method for making a semiconductor device is described. That method comprises converting a hydrophobic surface of a substrate into a hydrophilic surface, and forming a high-k gate dielectric layer on the hydrophilic surface.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: June 10, 2008
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Robert S. Chau
  • Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode
    Patent number: 7381608
    Abstract: A method for making a semiconductor device is described. That method comprises adding nitrogen to a silicon dioxide layer to form a nitrided silicon dioxide layer on a substrate. After forming a sacrificial layer on the nitrided silicon dioxide layer, the sacrificial layer is removed to generate a trench. A high-k gate dielectric layer is formed on the nitrided silicon dioxide layer within the trench, and a metal gate electrode is formed on the high-k gate dielectric layer.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: June 3, 2008
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Sangwoo Pae, Jack Kavalieros, Matthew V. Metz, Mark L. Doczy, Suman Datta, Robert S. Chau, Jose A. Maiz