Patents by Inventor Jack T. Kavalieros

Jack T. Kavalieros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240234422
    Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.
    Type: Application
    Filed: March 22, 2024
    Publication date: July 11, 2024
    Inventors: Cheng-Ying HUANG, Gilbert DEWEY, Anh PHAN, Nicole K. THOMAS, Urusa ALAAN, Seung Hoon SUNG, Christopher M. NEUMANN, Willy RACHMADY, Patrick MORROW, Hui Jae YOO, Richard E. SCHENKER, Marko RADOSAVLJEVIC, Jack T. KAVALIEROS, Ehren MANNEBACH
  • Publication number: 20240224536
    Abstract: Structures having layer select transistors for shared peripherals in memory are described. In an example, an integrated circuit structure includes a memory structure layer including a capacitor array coupled to a plurality of plate lines. A memory transistor layer is beneath the memory structure layer, the memory transistor layer including front end transistors coupled to corresponding capacitors of the capacitor array of the memory structure layer. A select transistor layer is over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end transistors. One or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Abhishek Anil SHARMA, Tahir GHANI, Jack T. KAVALIEROS, Anand S. MURTHY, Wilfred GOMES
  • Publication number: 20240222521
    Abstract: Technologies for ribbon field-effect transistors with variable nanoribbon numbers are disclosed. In an illustrative embodiment, a stack of semiconductor nanoribbons is formed, with each semiconductor nanoribbon having a source region, a channel region, and a drain region. Some or all of the channel regions can be selectively removed, allowing for the drive and/or leakage current to be tuned. In some embodiments, one or more of the semiconductor nanoribbons near the top of the stack can be removed. In other embodiments, one or more of the semiconductor nanoribbons at or closer to the bottom of the stack can be removed.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Evan A. Clinton, Rohit V. Galatage, Cheng-Ying Huang, Jack T. Kavalieros, Munzarin F. Qayyum, Marko Radosavljevic, Jami A. Wiedemer
  • Publication number: 20240213250
    Abstract: Embodiments disclosed herein include forksheet transistor transistors with self-aligned backbones. In an example, an integrated circuit structure includes a backbone including a lower backbone portion distinct from an upper backbone portion. A first vertical stack of nanowires is in lateral contact with a first side of the backbone. A second vertical stack of nanowires is in lateral contact with a second side of the backbone, the second side opposite the first side.
    Type: Application
    Filed: December 24, 2022
    Publication date: June 27, 2024
    Inventors: Shao Ming KOH, Sudipto NASKAR, Leonard P. GULER, Patrick MORROW, Richard E. SCHENKER, Walid M. HAFEZ, Charles H. WALLACE, Mohit K. HARAN, Jeanne L. LUCE, Dan S. LAVRIC, Jack T. KAVALIEROS, Matthew PRINCE, Lars LIEBMANN
  • Patent number: 12020929
    Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to manufacturing transistors that include a substrate, an epitaxial layer with a first side and a second side opposite the first side, where the first side and the second side of the epitaxial layer are substantially planar, where the second side of the epitaxial layer is substantially parallel to the first side, and where the first side of the epitaxial layer is directly coupled with a side of the substrate. In particular, the epitaxial layer may be adjacent to an oxide layer having a side that is substantially planar, where the second side of the epitaxial layer is adjacent to the side of the oxide layer, and the epitaxial layer was grown and the growth was constrained by the oxide layer.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 25, 2024
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron Lilak, Ehren Mannebach, Patrick Morrow, Anh Phan, Willy Rachmady, Hui Jae Yoo
  • Publication number: 20240204060
    Abstract: IC structures with nanoribbon stacks without dielectric protection caps for top nanoribbons, and associated methods and devices, are disclosed. An example IC structure includes a stack of nanoribbons, an opening over the top nanoribbon of the stack of nanoribbons, and a gate electrode material in the opening, where the opening has a first portion, a second portion, and a third portion, the second portion is between the first portion and the third portion, and where a width of a portion of the gate electrode material in the second portion is smaller than a width of a portion of the gate electrode material in the first portion. In such an IC structure, a gate insulator on the sidewalls of the first portion of the opening is materially discontinuous from a gate insulator on the sidewalls of the third portion of the opening.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Applicant: Intel Corporation
    Inventors: Rohit Galatage, Cheng-Ying Huang, Jack T. Kavalieros, Marko Radosavljevic, Mauro J. Kobrinsky, Jami Wiedemer, Munzarin Qayyum, Evan Clinton
  • Publication number: 20240204103
    Abstract: Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include multiple dipole materials, and related methods and devices. For example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. The transistor gate stack may include a gate electrode material and a gate dielectric material between the gate electrode material and the channel material, where the gate dielectric material includes a first dipole material and a second dipole material where one of the first and second dipole materials is a P-shifter dipole material and the other one is an N-shifter dipole material.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Applicant: Intel Corporation
    Inventors: Rohit Galatage, Cheng-Ying Huang, Dan S. Lavric, Sarah Atanasov, Shao Ming Koh, Jack T. Kavalieros, Marko Radosavljevic, Mauro J. Kobrinsky, Jami Wiedemer, Munzarin Qayyum, Evan Clinton
  • Publication number: 20240186127
    Abstract: An integrated circuit structure includes a source or drain region, and a contact coupled to the source or drain region. Sputter targets that include metals doped with the appropriate dopant types are used to deposit a conductive layer on the source or drain region that is annealed to form a region including metals and semiconductor materials between the source or drain region and the contact. A first dopant is within the source or drain region, and a second dopant is within the region. In one example, the first dopant is elementally different from the second dopant. In another example, the first dopant is elementally the same as the second dopant, wherein a concentration of the first dopant within a section of the source or drain region is within 20% of a concentration of the second dopant within the region.
    Type: Application
    Filed: December 28, 2023
    Publication date: June 6, 2024
    Applicant: Intel Corporation
    Inventors: Ilya V. Karpov, Aaron A. Budrevich, Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Dan S. Lavric
  • Publication number: 20240186398
    Abstract: Integrated circuit structures having cavity spacers, and methods of fabricating integrated circuit structures having cavity spacers, are described. For example, an integrated circuit structure includes a sub-fin structure over a stack of nanowires. A gate structure is vertically around the stack of nanowires. An internal gate spacer is between vertically adjacent ones of the nanowires and adjacent to the gate structure. A trench contact structure is laterally adjacent to a side of the gate structure. A cavity spacer is laterally between the gate structure and the trench contact structure.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 6, 2024
    Inventors: Aaron D. LILAK, Anh PHAN, Rishabh MEHANDRU, Stephen M. CEA, Patrick MORROW, Jack T. KAVALIEROS, Justin WEBER, Salim BERRADA
  • Patent number: 11996411
    Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Gilbert Dewey, Anh Phan, Nicole K. Thomas, Urusa Alaan, Seung Hoon Sung, Christopher M. Neumann, Willy Rachmady, Patrick Morrow, Hui Jae Yoo, Richard E. Schenker, Marko Radosavljevic, Jack T. Kavalieros, Ehren Mannebach
  • Patent number: 11996447
    Abstract: Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Matthew V. Metz, Willy Rachmady, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 11997847
    Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Shriram Shivaraman, Yih Wang, Tahir Ghani, Jack T. Kavalieros
  • Publication number: 20240170581
    Abstract: An integrated circuit structure includes a sub-fin having at least a first portion that is doped with a first type of dopant, and a second portion that is doped with a second type of dopant. A PN junction is between the first and second portions of the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. A first contact and a second contact comprise conductive material. In an example, the first contact and the second contact are respectively in contact with the first portion and the second portion of the sub-fin. A diode is formed based on the PN junction between the first and second portions, where the first contact is an anode contact of the diode, and the second contact is a cathode contact of the diode.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 23, 2024
    Applicant: Intel Corporation
    Inventors: Cheng-Ying Huang, Ayan Kar, Patrick Morrow, Charles C. Kuo, Nicholas A. Thomson, Benjamin Orr, Kalyan C. Kolluru, Marko Radosavljevic, Jack T. Kavalieros
  • Patent number: 11991873
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Yu-Wen Huang, Shu Zhou
  • Publication number: 20240153956
    Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 9, 2024
    Inventors: Seung Hoon SUNG, Cheng-Ying HUANG, Marko RADOSAVLJEVIC, Christopher M. NEUMANN, Susmita GHOSE, Varun MISHRA, Cory WEBER, Stephen M. CEA, Tahir GHANI, Jack T. KAVALIEROS
  • Patent number: 11978804
    Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Yih Wang
  • Patent number: 11978799
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: May 7, 2024
    Assignee: Tahoe Research, Ltd.
    Inventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
  • Patent number: 11980037
    Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Nazila Haratipour, Shriram Shivaraman, Sou-Chi Chang, Jack T. Kavalieros, Uygar E. Avci, Chia-Ching Lin, Seung Hoon Sung, Ashish Verma Penumatcha, Ian A. Young, Devin R. Merrill, Matthew V. Metz, I-Cheng Tung
  • Publication number: 20240145549
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Inventors: Siddharth CHOUKSEY, Glenn GLASS, Anand MURTHY, Harold KENNEL, Jack T. KAVALIEROS, Tahir GHANI, Ashish AGRAWAL, Seung Hoon SUNG
  • Publication number: 20240113161
    Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).
    Type: Application
    Filed: December 14, 2023
    Publication date: April 4, 2024
    Inventors: Willy RACHMADY, Cheng-Ying HUANG, Matthew V. METZ, Nicholas G. MINUTILLO, Sean T. MA, Anand S. MURTHY, Jack T. KAVALIEROS, Tahir GHANI, Gilbert DEWEY