Patents by Inventor Jack T. Kavalieros
Jack T. Kavalieros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250142935Abstract: Self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with reduced or removed caps, are described. In an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. A second gate electrode is over a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. A local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.Type: ApplicationFiled: December 27, 2024Publication date: May 1, 2025Inventors: Seung Hoon SUNG, Tristan TRONIC, Szuya S. LIAO, Jack T. KAVALIEROS
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Patent number: 12288803Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).Type: GrantFiled: December 14, 2023Date of Patent: April 29, 2025Assignee: Intel CorporationInventors: Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey
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Publication number: 20250107174Abstract: Neighboring gate-all-around integrated circuit structures having a conductive contact stressor between epitaxial source or drain regions are described. In an example, a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening conductive contact structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. The intervening conductive contact structure imparts a stress to the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.Type: ApplicationFiled: December 11, 2024Publication date: March 27, 2025Inventors: Siddharth CHOUKSEY, Jack T. KAVALIEROS, Stephen M. CEA, Ashish AGRAWAL, Willy RACHMADY
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Publication number: 20250107147Abstract: Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.Type: ApplicationFiled: September 27, 2023Publication date: March 27, 2025Applicant: Intel CorporationInventors: Mahmut Sami Kavrik, Uygar E. Avci, Pratyush P. Buragohain, Chelsey Dorow, Jack T. Kavalieros, Chia-Ching Lin, Matthew V. Metz, Wouter Mortelmans, Carl Hugo Naylor, Kevin P. O'Brien, Ashish Verma Penumatcha, Carly Rogan, Rachel A. Steinhardt, Tristan A. Tronic, Andrey Vyatskikh
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Patent number: 12255234Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.Type: GrantFiled: January 10, 2024Date of Patent: March 18, 2025Assignee: Intel CorporationInventors: Siddharth Chouksey, Glenn Glass, Anand Murthy, Harold Kennel, Jack T. Kavalieros, Tahir Ghani, Ashish Agrawal, Seung Hoon Sung
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Patent number: 12243875Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.Type: GrantFiled: January 10, 2024Date of Patent: March 4, 2025Assignee: Intel CorporationInventors: Seung Hoon Sung, Cheng-Ying Huang, Marko Radosavljevic, Christopher M. Neumann, Susmita Ghose, Varun Mishra, Cory Weber, Stephen M. Cea, Tahir Ghani, Jack T. Kavalieros
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Patent number: 12238913Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.Type: GrantFiled: January 31, 2023Date of Patent: February 25, 2025Assignee: Intel CorporationInventors: Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Bernhard Sell, Pei-hua Wang, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Umut Arslan, Travis W. Lajoie, Chieh-jen Ku
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Patent number: 12224202Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.Type: GrantFiled: July 21, 2023Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron Lilak, Ehren Mannebach, Patrick Morrow, Anh Phan, Willy Rachmady, Hui Jae Yoo
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Publication number: 20250022936Abstract: Self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with reduced or removed caps, are described. In an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. A second gate electrode is over a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. A local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.Type: ApplicationFiled: September 27, 2024Publication date: January 16, 2025Inventors: Seung Hoon SUNG, Tristan TRONIC, Szuya S. LIAO, Jack T. KAVALIEROS
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Patent number: 12199142Abstract: Neighboring gate-all-around integrated circuit structures having a conductive contact stressor between epitaxial source or drain regions are described. In an example, a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening conductive contact structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. The intervening conductive contact structure imparts a stress to the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.Type: GrantFiled: December 23, 2020Date of Patent: January 14, 2025Assignee: Intel CorporationInventors: Siddharth Chouksey, Jack T. Kavalieros, Stephen M. Cea, Ashish Agrawal, Willy Rachmady
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Patent number: 12191395Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.Type: GrantFiled: October 25, 2023Date of Patent: January 7, 2025Assignee: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung, Yih Wang, Tahir Ghani
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Patent number: 12191349Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.Type: GrantFiled: December 15, 2017Date of Patent: January 7, 2025Assignee: Intel CorporationInventors: Dipanjan Basu, Cory E. Weber, Justin R. Weber, Sean T. Ma, Harold W. Kennel, Seung Hoon Sung, Glenn A. Glass, Jack T. Kavalieros, Tahir Ghani
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Patent number: 12183831Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.Type: GrantFiled: September 29, 2017Date of Patent: December 31, 2024Assignee: Intel CorporationInventors: Van H. Le, Abhishek A. Sharma, Benjamin Chu-Kung, Gilbert Dewey, Ravi Pillarisetty, Miriam R. Reshotko, Shriram Shivaraman, Li Huey Tan, Tristan A. Tronic, Jack T. Kavalieros
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Patent number: 12176284Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.Type: GrantFiled: August 10, 2021Date of Patent: December 24, 2024Assignee: Intel CorporationInventors: Travis Lajoie, Abhishek Sharma, Juan Alzate-Vinasco, Chieh-Jen Ku, Shem Ogadhoh, Allen Gardiner, Blake Lin, Yih Wang, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani
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Publication number: 20240387634Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.Type: ApplicationFiled: May 20, 2024Publication date: November 21, 2024Inventors: Seung Hoon Sung, Seiyon Kim, Kelin J. Kuhn, Willy Rachmady, Jack T. Kavalieros
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Patent number: 12142689Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.Type: GrantFiled: September 8, 2022Date of Patent: November 12, 2024Assignee: Intel CorporationInventors: Sean Ma, Abhishek Sharma, Gilbert Dewey, Jack T. Kavalieros, Van H. Le
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Publication number: 20240355682Abstract: Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.Type: ApplicationFiled: July 2, 2024Publication date: October 24, 2024Applicant: Intel CorporationInventors: Varun Mishra, Stephen M. Cea, Cory E. Weber, Jack T. Kavalieros, Tahir Ghani
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Patent number: 12125917Abstract: Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.Type: GrantFiled: July 27, 2023Date of Patent: October 22, 2024Assignee: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey
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Patent number: 12119387Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.Type: GrantFiled: September 25, 2020Date of Patent: October 15, 2024Assignee: Intel CorporationInventors: Gilbert Dewey, Nazila Haratipour, Siddharth Chouksey, Jack T. Kavalieros, Jitendra Kumar Jha, Matthew V. Metz, Mengcheng Lu, Anand S. Murthy, Koustav Ganguly, Ryan Keech, Glenn A. Glass, Arnab Sen Gupta
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Patent number: 12087750Abstract: A stacked-substrate FPGA device is described in which a second substrate is stacked over a first substrate. Logic transistors (e.g., semiconductor devices and at least some conductive interconnections between them) are generally fabricated on (or over) a first substrate and memory transistors (e.g., SRAM cells and SRAM arrays) are generally fabricated on a second substrate over the first substrate. This has the effect of physically disposing elements of a CLB and a programmable switch on two different substrates. That is a first portion of a CLB and a programmable switch corresponding to logic transistors are on a first substrate and a second portion of these components of an FPGA corresponding to SRAM transistors is on a second substrate.Type: GrantFiled: September 25, 2018Date of Patent: September 10, 2024Assignee: Intel CorporationInventors: Abhishek A. Sharma, Willy Rachmady, Ravi Pillarisetty, Gilbert Dewey, Jack T. Kavalieros