Patents by Inventor Jack T. Kavalieros

Jack T. Kavalieros has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11658222
    Abstract: An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey, Shriram Shivaraman, Sean T. Ma, Benjamin Chu-Kung
  • Patent number: 11652606
    Abstract: A stacked-substrate advanced encryption standard (AES) integrated circuit device is described in which at least some circuits associated logic functions (e.g., AES encryption operations, memory cell access and control) are provided on a first substrate. Memory arrays used with the AES integrated circuit device (sometimes referred to as “embedded memory”) are provided on a second substrate stacked on the first substrate, thus forming a AES integrated circuit device on a stacked-substrate assembly. Vias are fabricated to pass through the second substrate, into a dielectric layer between the first substrate and the second substrate, and electrically connect to conductive interconnections of the AES logic circuits.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Willy Rachmady, Ravi Pillarisetty, Gilbert Dewey, Jack T. Kavalieros
  • Patent number: 11652047
    Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Ting Chen, Vinaykumar V. Hadagali
  • Publication number: 20230141914
    Abstract: Techniques are provided herein to form semiconductor devices having nanowires with an increased strain. A thin layer of silicon germanium or germanium tin can be deposited over one or more suspended nanoribbons. An anneal process may then be used to drive the silicon germanium or germanium tin throughout the one or more semiconductor nanoribbons, thus forming one or more nanoribbons with a changing material composition along the lengths of the one or more nanoribbons. In some examples, at least one of the one or more nanoribbons includes a first region at one end of the nanoribbon having substantially no germanium, a second region at the other end of the nanoribbon having substantially no germanium, and a third region between the first and second regions having a substantially uniform non-zero germanium concentration. The change in material composition along the length of the nanoribbon imparts a compressive strain.
    Type: Application
    Filed: November 10, 2021
    Publication date: May 11, 2023
    Applicant: Intel Corporation
    Inventors: Ashish Agrawal, Anand Murthy, Jack T. Kavalieros, Rajat K. Paul, Gilbert Dewey, Susmita Ghose, Seung Hoon Sung
  • Publication number: 20230147499
    Abstract: Techniques are provided herein to form semiconductor devices having strained channel regions. In an example, semiconductor nanoribbons of silicon germanium (SiGe) or germanium tin (GeSn) may be formed and subsequently annealed to drive the germanium or tin inwards along a portion of the semiconductor nanoribbons thus increasing the germanium or tin concentration through a central portion along the lengths of the one or more nanoribbons. Specifically, a nanoribbon may have a first region at one end of the nanoribbon having a first germanium concentration, a second region at the other end of the nanoribbon having substantially the same first germanium concentration (e.g., within 5%), and a third region between the first and second regions having a second germanium concentration higher than the first concentration. A similar material gradient may also be created using tin. The change in material composition (gradient) along the nanoribbon length imparts a compressive strain.
    Type: Application
    Filed: November 10, 2021
    Publication date: May 11, 2023
    Applicant: Intel Corporation
    Inventors: Ashish Agrawal, Anand Murthy, Jack T. Kavalieros, Rajat K. Paul, Gilbert Dewey, Seung Hoon Sung, Susmita Ghose
  • Publication number: 20230139255
    Abstract: A gate-all-around transistor device includes a body including a semiconductor material, and a gate structure at least in part wrapped around the body. The gate structure includes a gate electrode and a gate dielectric between the body and the gate electrode. The body is between a source region and a drain region. A first spacer is between the source region and the gate electrode, and a second spacer is between the drain region and the gate electrode. In an example, the first and second spacers include germanium and oxygen. The body can be, for instance, a nanoribbon, nanosheet, or nanowire.
    Type: Application
    Filed: November 2, 2021
    Publication date: May 4, 2023
    Applicant: Intel Corporation
    Inventors: Ashish Agrawal, Gilbert Dewey, Siddharth Chouksey, Jack T. Kavalieros, Cheng-Ying Huang
  • Publication number: 20230134379
    Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices, such as those having a stacked transistor configuration. In one example case, two different semiconductor devices may both be GAA transistors each having any number of nanoribbons extending in the same (e.g., horizontal) direction where one device is located vertically above the other device. An internal spacer structure extends between the nanoribbons of both devices along the vertical direction, where the spacer structure includes one or more rib features between the two devices. A gate structure that includes one or more gate dielectric layers and one or more gate electrode layers may be formed around the nanoribbons of both devices, in some cases. In other cases, a split-gate configuration is used where upper and lower gate structures are separated by an isolation structure. Forksheet transistors and other GAA configurations may be formed using the techniques as well.
    Type: Application
    Filed: November 3, 2021
    Publication date: May 4, 2023
    Applicant: Intel Corporation
    Inventors: Cheng-Ying Huang, Urusa Alaan, Susmita Ghose, Rambert Nahm, Natalie Briggs, Nicole K. Thomas, Willy Rachmady, Marko Radosavljevic, Jack T. Kavalieros
  • Patent number: 11640961
    Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: May 2, 2023
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Ravi Pillarisetty, Jack T. Kavalieros, Aaron D. Lilak, Willy Rachmady, Rishabh Mehandru, Kimin Jun, Anh Phan, Hui Jae Yoo, Patrick Morrow, Cheng-Ying Huang, Matthew V. Metz
  • Publication number: 20230126135
    Abstract: Techniques are provided herein to form a forksheet transistor device with a dielectric overhang structure. The dielectric overhang structure includes a dielectric layer that at least partially hangs over the nanoribbons of each semiconductor device in the forksheet transistor and is directly coupled to, or is an integral part of, the dielectric spine between the semiconductor devices. The overhang structure allows for a higher alignment tolerance when forming different work function metals over each of the different semiconductor devices, which in turn allows for narrower dielectric spines to be used. A first gate structure that includes a first work function metal may be formed around the nanoribbons of the n-channel device and a second gate structure that includes a second work function metal may be formed around the nanoribbons of the p-channel device in the forksheet arrangement.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 27, 2023
    Applicant: Intel Corporation
    Inventors: Christopher M. Neumann, Ashish Agrawal, Seung Hoon Sung, Marko Radosavljevic, Jack T. Kavalieros
  • Patent number: 11637185
    Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 25, 2023
    Assignee: Intel Corporation
    Inventors: Justin Weber, Harold Kennel, Abhishek Sharma, Christopher Jezewski, Matthew V. Metz, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Van H. Le, Arnab Sen Gupta
  • Patent number: 11631737
    Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: April 18, 2023
    Assignee: Intel Corporation
    Inventors: Sanaz K. Gardner, Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Jack T. Kavalieros, Chandra S. Mohapatra, Anand S. Murthy, Nadia M. Rahhal-Orabi, Nancy M. Zelick, Tahir Ghani
  • Patent number: 11626519
    Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: April 11, 2023
    Assignee: Intel Corporation
    Inventors: Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Marko Radosavljevic, Kent E. Millard, Marc C. French, Ashish Agrawal, Benjamin Chu-Kung, Ryan E. Arch
  • Patent number: 11626437
    Abstract: Embodiments herein describe techniques for an optical device including a substrate of a wafer. An image sensor device is formed on a front side of the substrate, while a plurality of posts of a metasurface lens are formed on a backside opposite to the front side of the substrate. A post of the plurality of posts includes a metasurface material that is transparent to light. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: April 11, 2023
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Kunjal Parikh, Jack T. Kavalieros
  • Patent number: 11626475
    Abstract: An improved trench capacitor structure is disclosed that allows for the formation of narrower capacitors. An example capacitor structure includes a first conductive layer on the sidewalls of an opening through a thickness of a dielectric layer, a capacitor dielectric layer on the first conductive layer, a second conductive layer on the capacitor dielectric layer, and a conductive fill material on the second conductive layer. The capacitor dielectric layer laterally extends above the opening and along a top surface of the dielectric layer, and the conductive fill material fills a remaining portion of the opening.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: April 11, 2023
    Assignee: Intel Corporation
    Inventors: Nazila Haratipour, Chia-Ching Lin, Sou-Chi Chang, Ian A. Young, Uygar E. Avci, Jack T. Kavalieros
  • Publication number: 20230100505
    Abstract: Embodiments disclosed herein include transistor devices and methods of forming such devices. In an embodiment, a transistor device comprises a first channel, wherein the first channel comprises a semiconductor material and a second channel above the first channel, wherein the second channel comprises the semiconductor material. In an embodiment, a first spacer is between the first channel and the second channel, and a second spacer is between the first channel and the second channel. In an embodiment, a first gate dielectric is over a surface of the first channel that faces the second channel, and a second gate dielectric is over a surface of the second channel that faces the first channel. In an embodiment, the first gate dielectric is physically separated from the second gate dielectric.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Ashish Verma PENUMATCHA, Sarah ATANASOV, Seung Hoon SUNG, Rahul RAMAMURTHY, I-Cheng TUNG, Uygar E. AVCI, Matthew V. METZ, Jack T. KAVALIEROS, Chia-Ching LIN, Kaan OGUZ
  • Publication number: 20230100952
    Abstract: Embodiments disclosed herein include transistors and transistor gate stacks. In an embodiment, a transistor gate stack comprises a semiconductor channel. In an embodiment, an interlayer (IL) is over the semiconductor channel. In an embodiment, the IL has a thickness of 1 nm or less and comprises zirconium. In an embodiment, a gate dielectric is over the IL, and a gate metal over the gate dielectric.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: I-Cheng TUNG, Ashish Verma PENUMATCHA, Seung Hoon SUNG, Sarah ATANASOV, Jack T. KAVALIEROS, Matther V. METZ, Uygar E. AVCI, Rahul RAMAMURTHY, Chia-Ching LIN, Kaan OGUZ
  • Publication number: 20230090092
    Abstract: An integrated circuit having a transistor architecture includes a first semiconductor body and a second semiconductor body. The first and second semiconductor bodies are arranged vertically (e.g., stacked configuration) or horizontally (e.g., forksheet configuration) with respect to each other, and separated from one another by insulator material, and each can be configured for planar or non-planar transistor topology. A first gate structure is on the first semiconductor body, and includes a first gate electrode and a first high-k gate dielectric. A second gate structure is on the second semiconductor body, and includes a second gate electrode and a second high-k gate dielectric. In an example, the first gate electrode includes a layer comprising a compound of silicon and one or more metals; the second gate structure may include a silicide workfunction layer, or not. In one example, the first gate electrode is n-type, and the second gate electrode is p-type.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Aaron D. Lilak, Orb Acton, Cheng-Ying Huang, Gilbert Dewey, Ehren Mannebach, Anh Phan, Willy Rachmady, Jack T. Kavalieros
  • Patent number: 11610894
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 21, 2023
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Yu-Wen Huang, Shu Zhou
  • Patent number: 11605565
    Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 14, 2023
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Willy Rachmady, Gilbert Dewey, Aaron Lilak, Kimin Jun, Brennen Mueller, Ehren Mannebach, Anh Phan, Patrick Morrow, Hui Jae Yoo, Jack T. Kavalieros
  • Patent number: 11594533
    Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron Lilak, Patrick Morrow, Anh Phan, Ehren Mannebach, Jack T. Kavalieros