Abstract: A driver circuit for driving light emitting diodes (LEDs). The driver circuit includes: a string of LEDs divided into n groups, the n groups of LEDs being electrically connected to each other in series, a downstream end of group m-1 being electrically connected to the upstream end of group m, where m is a positive number equal to or less than n. The driver circuit also includes a plurality of current regulating circuits, each of the current regulating circuits being coupled to the downstream end of a corresponding group at one end and coupled to the ground at the other end and including a sensor amplifier and a cascode having first and second transistors, each sensor amplifier being coupled to a different voltage source for providing a different reference voltage thereto.

Abstract: A driver circuit for driving light emitting diodes (LEDs). The driver circuit for driving light emitting diodes (LEDs) includes a string of LEDs divided into n groups. The n groups of LEDs are electrically connected to each other in series and the downstream end of group m?1 is electrically connected to the upstream end of group m, where m is a positive number equal to or less than n. The driver circuit also includes a plurality of current regulating circuits, where each of the current regulating circuits is coupled to a downstream end of a corresponding group and has at least one transistor and a detector for measuring a current flowing through the corresponding group.

Abstract: A driver circuit for driving light emitting diodes (LEDs). The driver circuit includes a string of LEDs divided into n groups and the n groups of LEDs is electrically connected to each other in series, where a downstream end of group m-1 is electrically connected to the upstream end of group m. The driver circuit also includes a power source coupled to an upstream end of group 1 and provides an input voltage. The driver circuit further includes current regulating circuits, where each of the current regulating circuits is coupled to the downstream end of the corresponding group at one end and coupled to a ground at the other end. Each of the current regulating circuits includes a sensor amplifier and a cascode having first and second transistors. The driver circuit also includes detectors, where each of the detectors detects a source voltage of the first transistor.

Abstract: A driver circuit for driving light emitting diodes (LEDs). The driver circuit includes a string of LEDs divided into n groups, the n groups of LEDs being electrically connected to each other in series, a downstream end of group m?1 being electrically connected to the upstream end of group m. The driver circuit also includes a power source coupled to an upstream end of group 1. The driver circuit further includes a plurality of current regulating circuits, where each current regulating circuit is coupled to the downstream end of a corresponding group at one end and coupled to a ground at another end and includes a sensor amplifier and a cascode having two transistors. The driver circuit also includes a phase control logic for sending a signal to each of the current regulating circuits to thereby control a current flow through each of the current regulating circuits.

Abstract: A driver circuit for driving light emitting diodes (LEDs). The driver circuit includes: a string of LEDs divided into n groups, the n groups of LEDs being electrically connected to each other in series, a downstream end of group m?1 being electrically connected to the upstream end of group m, where m is a positive number equal to or less than n. The driver circuit also includes a power source coupled to an upstream end of group 1 and operative to provide an input voltage and a plurality of current regulating circuits, each of the current regulating circuits being coupled to the downstream end of a corresponding group at one end and coupled to a ground at the other end and including a sensor amplifier and a cascode having first and second transistors.

Abstract: An embedded memory system that includes DRAM cells and logic transistors. The capacitor of the embedded memory responds to a positive bias voltage of ½ Vdd. The wordline driver of a p-channel access transistor applying the positive power supply voltage when the p-channel access FET is not being accessed and a voltage lower than the threshold voltage of the p-channel access FET is being accessed. For DRAM cells containing an n-channel access FET, the wordline driver applies either a negative voltage or the ground voltage to the n-channel access FET when the DRAM cell is not being accessed. A second voltage composed of Vdd and a boosted voltage is applied to the n-channel FET when the DRAM cell is being accessed.

Abstract: An apparatus and method reduce noise in a complex spectrum domain to extract a target signal from input signals containing noise and target speech. Noise estimation may be performed through a filter with a filter learning coefficient that is updated according to a prior-signal-to-noise ratio (prior-SNR). Also, noise estimation accuracy may be improved by using confidential weighted scores. The target signal may be extracted by representing candidates of the target signal as at least two circles in the complex spectrum domain using the estimated noise and then geometrically calculating the intersections of the circles.

Abstract: An embedded memory system that includes DRAM cells and logic transistors. The capacitor of the embedded memory responds to a positive bias voltage of ½ Vdd. The wordline driver of a p-channel access transistor applying the positive power supply voltage when the p-channel access FET is not being accessed and a voltage lower than the threshold voltage of the p-channel access FET is being accessed. For DRAM cells containing an n-channel access FET, the wordline driver applies either a negative voltage or the ground voltage to the n-channel access FET when the DRAM cell is not being accessed. A second voltage composed of Vdd and a boosted voltage is applied to the n-channel FET when the DRAM cell is being accessed.

Abstract: An apparatus for purifying polluted water is disclosed, which can naturally remove polluted water stagnated in a treatment tank. The apparatus includes a treatment tank and an infiltration tank. The treatment tank has an inlet at its one side, and first and second outlets at its other side. The treatment tank treats the polluted water that flows through the inlet and discharges the treated polluted water through the first outlet. The infiltration tank is connected to the second outlet and has a plurality of infiltration holes formed on the body thereof. The infiltration tank allows the treated polluted water that flows from the second outlet of the treatment tank to permeate into the ground though the plurality of infiltration holes. Since the polluted water stagnated in the treatment tank can be naturally released, odor due to decay of the polluted water and a subsequent insect infestation can be prevented. In addition, maintenance fees to maintain to the treatment tank can be reduced.

Abstract: An apparatus for purifying polluted water is disclosed, which can naturally remove polluted water stagnated in a treatment tank. The apparatus includes a treatment tank and an infiltration tank. The treatment tank has an inlet at its one side, and first and second outlets at its other side. The treatment tank treats the polluted water that flows through the inlet and discharges the treated polluted water through the first outlet. The infiltration tank is connected to the second outlet and has a plurality of infiltration holes formed on the body thereof. The infiltration tank allows the treated polluted water that flows from the second outlet of the treatment tank to permeate into the ground though the plurality of infiltration holes. Since the polluted water stagnated in the treatment tank can be naturally released, odor due to decay of the polluted water and a subsequent insect infestation can be prevented. In addition, maintenance fees to maintain to the treatment tank can be reduced.

Abstract: An array of memory cells that require periodic refresh is operated in a single-cell mode during normal operating conditions. Upon receiving an asserted standby control signal from an accessing memory client, the array enters a standby mode from the normal operating conditions. The standby mode can be specified as a differential-cell mode, a single-cell mode or a non-retentive mode. To enter the differential-cell standby mode, data stored in the single-cell mode is converted to a differential-cell mode. In this conversion, half of the data stored in the single-cell mode is saved, while the other half is discarded. In the differential-cell standby mode, refresh operations are performed less frequently than in the normal operating mode, thereby conserving power. The external clock signal provided by the accessing memory client can be disabled during the differential-cell standby mode, as a local clock signal is provided to implement the refresh operations during standby mode.

Abstract: An array of memory cells that require periodic refresh is operated in a single-cell mode during normal operating conditions. Upon receiving an asserted standby control signal from an accessing memory client, the array enters a standby mode from the normal operating conditions. The standby mode can be specified as a differential-cell mode, a single-cell mode or a non-retentive mode. To enter the differential-cell standby mode, data stored in the single-cell mode is converted to a differential-cell mode. In this conversion, half of the data stored in the single-cell mode is saved, while the other half is discarded. In the differential-cell standby mode, refresh operations are performed less frequently than in the normal operating mode, thereby conserving power. The external clock signal provided by the accessing memory client can be disabled during the differential-cell standby mode, as a local clock signal is provided to implement the refresh operations during standby mode.

Abstract: Disclosed is a method for preparing a CLA-enriched structured lipid by a transesterification of medium chain triglyceride (MCT) with ester or free fatty acid form of CLA using lipases, and use of the same. It has been known that CLA mainly exists in an acid form, and has various beneficial biological activities, but rapid oxidation property during storage. And also, animal fat or plant oil, widely ingested by animals or humans, is naturally produced as an acylglycerol form containing various fatty acids. The CLA-containing structured lipid is manufactured by mixing free or ester form of CLA with acylglyceride at a molar ratio of 1:1˜1:5, adding immobilized lipase of 2.2˜20% by weight of CLA and acylglyceride to the mixture with a solvent, and incubating at 35˜75° C. for 1-36 hours.

Abstract: A solid state image sensor includes a semiconductor substrate and a plurality of transfer lines over the substrate and receiving clock signals, at least one of the plurality of transfer lines having a transparent conductive material. A plurality of transfer electrodes are connected to the transfer lines and a plurality of photoelectric conversion regions under a surface of the substrate generate image signals. A plurality of charge transfer regions under the surface of the substrate transfer the image signals from the photoelectric conversion regions in response to the clock signals from the transfer lines.

Abstract: An improved voltage level shifting circuit which is capable of increasing a level shifting speed and reducing a current consumption and layout area by decreasing a pull-up capacity of the pull-up PMOS transistors in a side in which a voltage level is shifted to a low level and increasing a pull-up capacity through the NMOS transistors in a side in which a voltage level is shifted to a high level.

Abstract: A semiconductor memory device having a sub-word line driving circuit overcoming disadvantages of a conventional semiconductor memory device having a sub-word line driving circuit in that it requires additional NMOS transistors with their gates applied with a predecoding signal in order to connect all sub-word lines to the ground which may be floated during the operation of the sub-word line driving circuit, and thus a layout of the device is complicated and a size of the memory chip is increased, can simplify the device layout and reduce the memory chip size by using the NMOS transistor connecting the adjacent sub-word lines which are applied with an identical predecoding signal but receive different inverted global word line enable signals.

Abstract: The row decoder includes an internal node and an output node. A decoding unit receives a plurality of externally-applied address signals and pulls down the internal node to a logic low voltage when the plurality of address signals have an active state. A latch unit pulls up the output node to a logic high voltage in response to the pulling-down of the internal node by the decoding unit, pulls down the output node to the logic low voltage when the internal node is at the logic high voltage, and reduces a voltage at the internal node to a voltage less than the logic high voltage and greater than the logic low voltage based on a selection signal.

Abstract: A word line driver for a semiconductor memory device includes a row decoder for generating a block select signal and driving a main word line in accordance with an address signal, a sub word line enable unit for generating a main decoding signal in accordance with the address signal, a word decoder driver for buffering the main decoding signal and transmitting the main decoding signal to a memory cell block, a block word decoder driver for enabling a sub decoding signal in the memory cell block in accordance with the block select signal and the main decoding signal, and a sub word line driver for driving a sub word line in accordance with the sub decoding signal and the main word line driven by the row decoder.

Abstract: A solid state image sensor includes a semiconductor substrate and a plurality of transfer lines over the substrate and receiving clock signals, at least one of the plurality of transfer lines having a transparent conductive material. A plurality of transfer electrodes are connected to the transfer lines and a plurality of photoelectric conversion regions under a surface of the substrate generate image signals. A plurality of charge transfer regions under the surface of the substrate transfer the image signals from the photoelectric conversion regions in response to the clock signals from the transfer lines.

Abstract: A memory device of the present invention includes a plurality of bitlines and main wordlines formed in first and second directions, respectively, to form a matrix, and a plurality of memory cells coupled to each bitline. A first decoder decodes first address signals and provides first decoded signals to the plurality of main wordlines. A second decoder decodes second address signals and provides second decoded signals. The memory device also includes n-th number of groups of drivers, and each group has a plurality of sub-drivers formed in a third direction to receive a corresponding second decoded signal. Each sub-driver has a plurality of selection lines coupled to corresponding memory cells, and a plurality of sense amplifiers is coupled to said plurality of bitlines, wherein more than two bitlines are formed between adjacent groups of drivers.