Abstract: The inventive concept provides a substrate treating apparatus. The substrate treating apparatus comprising: a treating vessel including an outer cup and an inner cup placed in an inner side of the outer cup, the inner cup and the outer cup in combination defining a recollecting route for a recollecting a liquid; a rotatable spin head placed within the treating vessel on which a cleaning jig is placed; wherein the treating vessel comprises a first protrusion protruding from an inner side surface of the outer cup to direct a cleaning liquid scattering from the cleaning jig toward a surface of the inner cup.

Abstract: A baffle including a base plate disposed in a central portion of a showerhead in an apparatus for processing a substrate. An extension plate is movably connected to a planar surface of the base plate. The extension plate is configured to extend and contract radially from the base plate to change a diameter of the baffle.

Abstract: A gas processing system according to an embodiment of the present invention includes a heater which is configured to increase a temperature of liquefied gas compulsorily vaporized by a forcing vaporizer before the liquefied gas is joined with Boil Off Gas (BOG) compressed by a BOG compressor.

Abstract: Disclosed are an LCD device and a method of manufacturing the same, in which a passivation layer and a pixel electrode are simultaneously formed by a single mask process using a half tone mask, and thus, manufacturing efficiency increases, and a defective contact due to loss of the pixel electrode can be prevented in a pad area. The LCD device includes a pad part including a pad area and a contact area. The LCD device includes a pixel pad formed in the pad area, a pixel bar formed in the contact area, and a bridge layer contacting the pixel pad with the pixel bar. The bridge layer is formed as a single layer or multi layers, and formed of one or more of a transparent conductive material and an opaque conductive material.

Abstract: A gas processing system according to an embodiment of the present invention includes a heater which is configured to increase a temperature of liquefied gas compulsorily vaporized by a forcing vaporizer before the liquefied gas is joined with Boil Off Gas (BOG) compressed by a BOG compressor.

Abstract: Disclosed are an LCD device and a method of manufacturing the same, in which a passivation layer and a pixel electrode are simultaneously formed by a single mask process using a half tone mask, and thus, manufacturing efficiency increases, and a defective contact due to loss of the pixel electrode can be prevented in a pad area. The LCD device includes a pad part including a pad area and a contact area. The LCD device includes a pixel pad formed in the pad area, a pixel bar formed in the contact area, and a bridge layer contacting the pixel pad with the pixel bar. The bridge layer is formed as a single layer or multi layers, and formed of one or more of a transparent conductive material and an opaque conductive material.

Abstract: Disclosed are an LCD device and a method of manufacturing the same, in which a passivation layer and a pixel electrode are simultaneously formed by a single mask process using a half tone mask, and thus, manufacturing efficiency increases, and a defective contact due to loss of the pixel electrode can be prevented in a pad area. The LCD device includes a pad part including a pad area and a contact area. The LCD device includes a pixel pad formed in the pad area, a pixel bar formed in the contact area, and a bridge layer contacting the pixel pad with the pixel bar. The bridge layer is formed as a single layer or multi layers, and formed of one or more of a transparent conductive material and an opaque conductive material.

Abstract: There is provided a power semiconductor device including: a first semiconductor region of a first conductivity type; second semiconductor regions formed in the first semiconductor region and being of a second conductivity type; a well region formed above the second semiconductor regions and being of the second conductivity type; and a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers formed from a lower portion of the device extending a in a direction of height of the device, and in the case that the widest width of the of the second semiconductor region of the nth layer is Pn, P1<Pn (n?2).

Abstract: A power semiconductor device may include a first conductivity type semiconductor substrate, a super-junction portion disposed on the first conductivity type semiconductor substrate and including a first conductivity type pillar and a second conductivity type pillar arranged in an alternating manner, and a three-dimensional (3D) gate portion disposed on the first conductivity type pillar. The 3D gate portion is disposed on the first conductivity type pillar to reduce the widths of the first and second conductivity type pillars, thereby effectively reducing a device size.

Abstract: Provided is a method for forming a pattern of an organic thin film semiconductor element. The method for forming a pattern of an organic thin film semiconductor element includes: preparing a mold structure having a groove; positioning the mold structure on an upper part of a substrate to enable the groove and the substrate to form a pipe; supplying an organic semiconductor material to a surface of the substrate; and hardening the organic semiconductor material.

Abstract: A power semiconductor device may include: a first conductive type drift layer in which trench gates are formed; a second conductive type well region formed on the drift layer so as to contact the trench gate; a first conductive type source region formed on the well region so as to contact the trench gate; and a device protection region formed below a height of a lowermost portion of the source region in a height direction.

Abstract: A method of manufacturing a semiconductor device may include: preparing a substrate formed of SiC; depositing crystalline or amorphous silicon (Si) on one surface of the substrate to form a first semiconductor layer; and performing a heat treatment under a nitrogen atmosphere to form a second semiconductor layer formed of SiCN between the substrate and the first semiconductor layer.

Abstract: Disclosed herein is a semiconductor device including: a source electrode formed on one side of an N-type AlGaN layer; N-type and P-type AlGaN layers formed on the other side of the P-type AlGaN layer and formed in a direction perpendicular to the source electrode; a gate electrode formed on one side of the N-type and P-type AlGaN layers; and a drain electrode formed on the other side of the N-type and P-type AlGaN layers.

Abstract: A power semiconductor device may include a first conductivity type first semiconductor region; a second conductivity type second semiconductor region formed on an upper portion of the first semiconductor region; a first conductivity type third semiconductor region formed in an upper inner side of the second semiconductor region; a trench gate formed to penetrate through a portion of the first semiconductor region from the third semiconductor region; and a first conductivity type fourth semiconductor region formed below the second semiconductor region while being spaced apart from the trench gate.

Abstract: A power semiconductor device may include: an active region in which a current flows through a channel formed when the device being turned on; a termination region disposed around the active region; a first semiconductor region of a first conductive type disposed in the termination region in a direction from the active region to the termination region; and a second semiconductor region of a second conductive type disposed in the termination region in the direction from the active region to the termination region, the first semiconductor region and the second semiconductor region being disposed alternately.

Abstract: A power semiconductor device may include: a base substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench.

Abstract: A power semiconductor device may include a first conductivity type semiconductor substrate, a super-junction portion disposed on the first conductivity type semiconductor substrate and including a first conductivity type pillar and a second conductivity type pillar arranged in an alternating manner, and a three-dimensional (3D) gate portion disposed on the first conductivity type pillar. The 3D gate portion is disposed on the first conductivity type pillar to reduce the widths of the first and second conductivity type pillars, thereby effectively reducing a device size.

Abstract: A power semiconductor device may include a drift region including a base layer and a surface semiconductor layer disposed on the base layer and having a first conductivity type; a field insulating layer disposed on the base layer, embedded in the surface semiconductor layer, and including an opening portion; and a collector region disposed below the base layer and having a second conductivity type. The field insulating layer is formed in the drift region to limit movement of holes, whereby conduction loss of the power semiconductor device may be significantly decreased.

Abstract: A power semiconductor device may include: an n-drift part; a gate disposed in an upper portion of the n-drift part; an active part disposed to be in contact with the gate; an emitter part disposed in the active part and disposed to be in contact with the gate; an inactive part disposed to be spaced apart from the active part; a floating part disposed in the inactive part; and a dummy gate disposed to surround the inactive part in order to prevent a hole pass between the active part and the inactive part.

Abstract: A power semiconductor device may include: a first conductivity-type first semiconductor region; a second conductivity-type second semiconductor region disposed above the first semiconductor region; a trench gate penetrating through the second semiconductor region and a portion of the first semiconductor region; a third semiconductor region disposed on both sides of the trench gate and disposed on an inner side of an upper portion of the second semiconductor region; and a device protective region disposed in the third semiconductor region.