Abstract: Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.

Abstract: Disclosed herein is a power semiconductor device. The power semiconductor device includes a second conductive type first junction termination extension (JTE) layer that is formed so as to be in contact with one side of the second conductive type well layer, a second conductive type second JTE layer that is formed on the same line as the second conductive type first JTE layer, and is formed so as to be spaced apart from the second conductive type first JTE layer in a length direction of the substrate, and a poly silicon layer that is formed so as to be in contact with the second conductive type well layer and an upper portion of the second conductive type first JTE layer.

Abstract: Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.

Abstract: A power semiconductor device may include: a first conductivity-type first semiconductor region; a resurf region disposed in the first semiconductor region and including first conductivity-type second semiconductor regions and second conductivity-type third semiconductor regions alternately disposed in a width direction; a first conductivity-type first cover region disposed in the first semiconductor region, disposed to be contiguous with an upper surface of the resurf region, and having an impurity concentration higher than that of the first semiconductor region; a second conductivity-type fourth semiconductor region disposed above the first semiconductor region; a first conductivity-type fifth semiconductor region disposed on an inner side of an upper portion of the fourth semiconductor region; and a trench gate disposed to penetrate from the fifth semiconductor region to a portion of an upper portion of the first semiconductor region and including a gate insulating layer and a conductive material.

Abstract: A power semiconductor device may include: an active region in which a current flows through a channel formed when the device being turned on; a termination region disposed around the active region; a first semiconductor region of a first conductive type disposed in the termination region in a direction from the active region to the termination region; and a second semiconductor region of a second conductive type disposed in the termination region in the direction from the active region to the termination region, the first semiconductor region and the second semiconductor region being disposed alternately.

Abstract: A power semiconductor device may include: a first conductivity-type drift region in which a plurality of trench gates each including a gate insulating layer disposed on a surface thereof and a conductive material filling the interior thereof are disposed; a second conductivity-type body region disposed on an inner side of an upper portion of the drift region and disposed to be in contact with the trench gate; a first conductivity-type emitter region disposed on an inner side of an upper portion of the body region and disposed to be in contact with the trench gate; and a hole accumulation region disposed in the drift region, disposed below the body region, and disposed between the trench gates.

Abstract: A power semiconductor device may include: a first conductivity-type first semiconductor layer; a second conductivity-type second semiconductor layer disposed above the first semiconductor layer; and a heat dissipation trench disposed to penetrate from an upper surface of the second semiconductor layer into a portion of the second semiconductor layer and having an insulating layer disposed on a surface thereof.

Abstract: A power semiconductor device may include a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and formed in an upper portion of the first semiconductor region; a third semiconductor region having a first conductivity type and formed in an upper portion of the second semiconductor region; and a trench gate formed by penetrating from the third semiconductor region to the first semiconductor region. A portion of at least one of the first semiconductor region, the second semiconductor region, and the third semiconductor region may include a device protection material of which a conduction band has a main state and a satellite state in an E-k diagram, and a curvature of the device protection material in the satellite state may be lower than a curvature thereof in the main state in the E-k diagram.

Abstract: A provided a power semiconductor device may include: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type formed on the first semiconductor region; a plurality of trench gates formed to penetrate through the second semiconductor region and lengthily formed in one direction; and a third semiconductor region of the first conductive type formed on the second semiconductor region, formed at least partially in a length direction between the plurality of trench gates, and formed to contact one side of an adjacent trench gate in a width direction.

Abstract: A power semiconductor device may include: a semiconductor laminate formed by stacking a plurality of semiconductor layers each having an emitter metal layer formed on a top thereof and a collector metal layer formed on a bottom thereof; an insulating layer interposed between the semiconductor layers; and a first external electrode and a second external electrode formed on sides of the semiconductor laminate. The first external electrode is electrically connected to the emitter metal layer, and the second external electrode is electrically connected to the collector metal layer.

Abstract: A power semiconductor device may include: an active region having a channel formed therein when the power semiconductor device is turned on, the channel allowing a current to flow therethrough; a termination region formed around the active region; first trenches formed in the active region, each first trench having an insulating layer formed on a surface thereof and filled with a conductive material; and second trenches formed in the termination region, each second trench having an insulating layer formed on a surface thereof and filled with a conductive material.

Abstract: A method of manufacturing a semiconductor device may include: preparing a substrate formed of SiC; depositing crystalline or amorphous silicon (Si) on one surface of the substrate to form a first semiconductor layer; and performing a heat treatment under a nitrogen atmosphere to form a second semiconductor layer formed of SiCN between the substrate and the first semiconductor layer.

Abstract: A power semiconductor device may include: a first conductivity-type first semiconductor region; a second conductivity-type second semiconductor region disposed above the first semiconductor region; a trench gate penetrating through the second semiconductor region and a portion of the first semiconductor region; a third semiconductor region disposed on both sides of the trench gate and disposed on an inner side of an upper portion of the second semiconductor region; and a device protective region disposed in the third semiconductor region.

Abstract: A power semiconductor device may include: an active region having a current flowing through a channel formed therein at the time of a turn-on operation of the power semiconductor device; a termination region formed in the vicinity of the active region; a plurality of trenches formed in a length direction of the active region; and a hole accumulating region formed in the active region and below the channel and having a first conductivity type. A trench disposed at a boundary between the termination region and the active region has a depth shallower than that of a trench adjacent thereto.

Abstract: A power semiconductor device may include: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and formed on the first semiconductor region; a third semiconductor region having the first conductivity type and formed in an upper portion of the second semiconductor region; a trench gate formed to penetrate from the third semiconductor region to the first semiconductor region, having a gate insulating layer formed on a surface thereof, and filled with a conductive material; and a fourth semiconductor region having the second conductivity type and formed to penetrate through the second semiconductor region.

Abstract: A power semiconductor device may include: an active region having a current flowing through a channel formed therein at the time of a turn-on operation of the power semiconductor device; a termination region formed in the vicinity of the active region; a plurality of first trenches formed lengthwise in one direction in the active region; and at least one or more second trenches formed lengthwise in one direction in the termination region. The second trench has a depth deeper than that of the first trench.

Abstract: A power semiconductor device may include: a first semiconductor layer having a first conductivity type; a second semiconductor layer formed on the first semiconductor layer, having a concentration of impurities higher than that of the first semiconductor layer, and having the first conductivity type; a third semiconductor layer formed on the second semiconductor layer and having a second conductivity type; a fourth semiconductor layer formed in an upper surface of the third semiconductor layer and having the first conductivity type; and trench gates penetrating from the fourth semiconductor layer into a portion of the first semiconductor layer and having gate insulating layers formed on surfaces thereof. The trench gates have a first gate, a second gate, and a third gate are sequentially disposed from a lower portion thereof, and the first gate, the second gate, and the third gate are insulated from each other by gate insulating films.

Abstract: A power semiconductor device may include a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type formed on an upper portion of the first semiconductor region, a third semiconductor region having a first conductivity type formed in an inner portion of an upper portion of the second semiconductor region, a trench gate formed to penetrate from the third semiconductor region to the first semiconductor region and including a first insulating layer formed on a surface thereof, and a second insulating layer formed in a lower portion of the trench gate.

Abstract: A power semiconductor device may include: an active region having a current flowing through a channel formed therein at the time of a turn-on operation of the power semiconductor device; an termination region formed in the vicinity of the active region; a plurality of trenches formed in a length direction of the active region; a first conductivity type hole accumulating region formed below the channel in the active region; and a first conductivity type electric field limiting region formed in the termination region. The electric field limiting region is formed so as to at least partially cover a trench positioned at a boundary between the active region and the termination region.

Abstract: A power semiconductor device may include a first conductivity type first semiconductor region; a second conductivity type second semiconductor region formed on an upper portion of the first semiconductor region; a first conductivity type third semiconductor region formed in an upper inner side of the second semiconductor region; a trench gate formed to penetrate through a portion of the first semiconductor region from the third semiconductor region; and a first conductivity type fourth semiconductor region formed below the second semiconductor region while being spaced apart from the trench gate.