Abstract: Provided are a semiconductor device and a semiconductor package. The semiconductor device includes semiconductor device includes a semiconductor substrate having a first side and a second side. A front-side structure including an internal circuit is disposed on the first side of the semiconductor substrate. A passivation layer is disposed on the second side of the semiconductor substrate. A through-via structure passes through the semiconductor substrate and the passivation layer. A back-side conductive pattern is disposed on the second side of the semiconductor substrate. The back-side conductive pattern is electrically connected to the through-via structure. An alignment recessed area is disposed in the passivation layer. An insulating alignment pattern is disposed in the alignment recessed area.

Abstract: A liquid crystal display device may include a substrate. The liquid crystal display device may further include a pixel electrode disposed on the substrate. The liquid crystal display device may further include a common electrode overlapping the pixel electrode, wherein a liquid crystal injection hole is formed through at least the common electrode. The liquid crystal display device may further include a liquid crystal layer disposed between the pixel electrode and the common electrode. The liquid crystal display device may further include a light-blocking element disposed inside the liquid crystal injection hole.

Abstract: Provided is an integrated circuit device including a through-silicon-via (TSV) structure and a method of manufacturing the integrated circuit device. The integrated circuit device includes a semiconductor structure including a substrate and an interlayer insulating film, a TSV structure passing through the substrate and the interlayer insulating film, a via insulating film substantially surrounding the TSV structure, and an insulating spacer disposed between the interlayer insulating film and the via insulating film.

Abstract: A liquid crystal display includes a first substrate including pixels arranged in m columns by n rows, n data lines disposed, m gate lines arranged substantially parallel to the data lines, n data distribution lines arranged to cross the m gate lines and electrically connected to the data lines, respectively, source driving chips disposed on a first portion of the first substrate, and a gate driver disposed on a second portion of the first substrate. Each of the data distribution lines is connected to a subset of the pixels arranged in a corresponding row, and each of the gate lines is connected to a subgroup of the pixels arranged in a corresponding column. The source driving chips apply data signals to the pixels through the first data lines and the data distribution lines, and the gate driver applies gate signals to the pixels through the gate lines.

Abstract: A transparent display apparatus includes a display panel including a plurality of pixels arranged in rows and columns, a plurality of gate lines, a plurality of data lines including first and second data lines, a gate driver, and a data driver. Each of the pixels comprises sub-pixels arranged in a row direction, each gate line is operatively coupled to sub-pixels arranged in a corresponding row, and each first and second data line is operatively coupled to sub-pixels arranged in a corresponding column. The gate driver sequentially applies a gate signal to the pixels through the gate lines. The data driver applies sub-data signals to the sub-pixels through the first data lines, and applies down data signals to the sub-pixels through the second data lines. Each of the down data signals has a voltage level lower than a voltage level of a corresponding sub-data signal.

Abstract: A liquid crystal display includes a first substrate including pixels arranged in m columns by n rows, n data lines disposed, m gate lines arranged substantially parallel to the data lines, n data distribution lines arranged to cross the m gate lines and electrically connected to the data lines, respectively, source driving chips disposed on a first portion of the first substrate, and a gate driver disposed on a second portion of the first substrate. Each of the data distribution lines is connected to a subset of the pixels arranged in a corresponding row, and each of the gate lines is connected to a subgroup of the pixels arranged in a corresponding column. The source driving chips apply data signals to the pixels through the first data lines and the data distribution lines, and the gate driver applies gate signals to the pixels through the gate lines.

Abstract: A liquid crystal display device may include a substrate. The liquid crystal display device may further include a pixel electrode disposed on the substrate. The liquid crystal display device may further include a common electrode overlapping the pixel electrode, wherein a liquid crystal injection hole is formed through at least the common electrode. The liquid crystal display device may further include a liquid crystal layer disposed between the pixel electrode and the common electrode. The liquid crystal display device may further include a light-blocking element disposed inside the liquid crystal injection hole.

Abstract: A method for exemplar-based inpainting using a Laplacian pyramid in a multi-scale space is provided, which is capable of reflecting structural features and texture features simultaneously every time inpainting is performed. The exemplar-based inpainting method using the Laplacian pyramid in the multi-scale space includes constructing a Laplacian pyramid image including a plurality of levels using an input image and performing inpainting reflecting the structural features of a low frequency region and the texture features of a high frequency region using the Laplacian pyramid image.

Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.

Abstract: A display substrate includes a base substrate, a thin-film transistor (TFT), a color filter and a pixel electrode. The TFT is on the base substrate. The color filter is on the base substrate including the TFT and in contact with the base substrate. The pixel electrode is on the color filter and in electrical connection to a drain electrode of the TFT.

Abstract: A semiconductor integrated circuit device includes a TSV (Through Silicon Via) extending through a substrate, a first well in the substrate adjacent a first surface of the substrate, a gate of an active device on the first well, a charging protection well, and a charging protection gate on the charging protection well. The charging protection well is disposed in the substrate adjacent the first surface of the substrate, is interposed between the TSV hole and the first well, and surrounds the TSV hole. The charging protection gate prevents the gate of the active device from being damaged when the TSV is formed especially when using a plasma etch process to form a TSV hole in the substrate.

Abstract: A display device includes gate lines, data lines, first wires and second wires extending in the directions of the gate lines and data lines, and pixels having a first subpixel and a second subpixel each. The first subpixel has a first subpixel electrode and a first switching element, and the second subpixel has a second subpixel electrode and second and third switching elements. The control terminals of the three switching elements are connected to the same gate line, and the input terminals of the first and second switching elements are connected to the same data line. The first and second switching elements have output terminals connected to the first and second subpixel electrodes, respectively. The second switching element's output terminal connects to the third switching element, which has an output terminal connected to a second wire. The first wires and the second wires are connected in a pixel.

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad.

Abstract: An integrated circuit device includes a semiconductor substrate having first and second semiconductor regions therein, a gate trench in the first semiconductor region and a gate electrode in the gate trench. The gate electrode has an upper surface below a surface of the semiconductor substrate. A semiconductor well region is provided in the second semiconductor region. A capacitor trench extends in the semiconductor well region and an upper capacitor electrode extends in the capacitor trench. An electrical interconnect (e.g., conductive plug) is provided, which is electrically connected to the upper capacitor electrode at an interface therebetween. This interface has an upper surface below the surface of the semiconductor substrate.

Abstract: Integrated circuit (IC) devices are provided including: a first multi-layer wiring structure including a plurality of first wiring layers in a first region of a substrate at different levels and spaced apart from one another, and a plurality of first contact plugs between the plurality of first wiring layers and connected to the plurality of first wiring layers; a through-silicon via (TSV) landing pad including a first pad layer in a second region of the substrate at a same level as that of at least one first wiring layer from among the plurality of first wiring layers, and a second pad layer at a same level as that of at least one first contact plug from among the plurality of first contact plugs and contacts the first pad layer; a second multi-layer wiring structure on the TSV landing pad; and a TSV structure that passes through the substrate and is connected to the second multi-layer wiring structure through the TSV landing pad.

Abstract: A display panel includes: a first base substrate on which a plurality of pixel areas are defined; a color filter layer including a plurality of color filters respectively in the plurality of pixel areas of the first base substrate, where four color filters having different colors are respectively in four pixel areas adjacent to each other; a plurality of pixel electrodes on the color filter layer, respectively in the plurality of pixel areas and electrically insulated from each other; a first area including a contact point at which the four adjacent pixel areas meet; a second base substrate which is combined with the first base substrate and faces the second base substrate; and a reference electrode on one of the first and second base substrates. At least one color filter among the four adjacent color filters includes a protruding part which overlaps the first area.

Abstract: A thin-film transistor (TFT) substrate includes a base substrate, a test pad and a test pad line. The base substrate includes a display area including a data line and a TFT, a peripheral area including a common voltage line, and a test area disposed outside of the peripheral area. The test pad is disposed in the test area and electrically connected to the data line. The test pad line connects the data line with the test pad and crosses the common voltage line.

Abstract: Disclosed is a liquid crystal display including: a first substrate; a gate line disposed on the first substrate; a data line disposed on the gate line; and a thin film transistor connected to the gate line and the data line. A plurality of color filters is disposed on the thin film transistor and the data line. A capping layer is disposed on the plurality of color filters. A shielding electrode is disposed on the capping layer. An insulating layer is disposed on the capping layer and includes a first opening extending to a part of the shielding electrode. A light blocking member is disposed on the insulating layer and the shielding electrode. The shielding electrode is disposed in a part corresponding to the data line. Adjacent color filters among the plurality of color filters overlap with each other in the part corresponding to the data line. The first opening is disposed in a part corresponding to the region where the adjacent color filters overlap with each other.

Abstract: A display panel includes a first display substrate, a second display substrate facing the first display substrate and being coupled to the first display substrate, a liquid crystal layer interposed between the first display substrate and the second display substrate, an alignment layer disposed in a display area of at least one of the first and second display substrates, and a partition wall disposed in a peripheral area surrounding the display area of the first or second display substrate. The partition wall includes a body and a capping layer that covers an upper surface of the body. A width of the upper surface of the body is smaller than a width of the capping layer disposed on the body.

Abstract: A display panel includes a base substrate, a driving circuit, and a roof layer defining a cavity. A color filter is disposed on the base substrate to at least partially cover the driving circuit. The color filter is disposed at least on a pixel area and includes a depression positioned at least partially within a circuit area. A black matrix is disposed upon the depression of the color filter. The black matrix being upon the depression allows an inlet portion of the cavity to remain greater than a certain cross-sectional area.