Patents by Inventor Jae-Hyuk Im

Jae-Hyuk Im has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12132140
    Abstract: An ink includes a solvent, and light-emitting elements dispersed in the solvent, each of the light-emitting elements comprising semiconductor layers and an insulating film partially surrounding outer surfaces of the semiconductor layers, wherein the solvent has Hansen solubility parameters of a polarity parameter between about 4 and about 9 and a hydrogen bonding parameter between about 6 and about 11.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: October 29, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyo Jin Ko, Duk Ki Kim, Yong Hwi Kim, Jun Bo Sim, Na Mi Hong, Jong Hyuk Kang, Gyu Bong Kim, Hoi Lim Kim, Sae Na Yun, Chang Hee Lee, Hyun Deok Im, Eun A Cho, Jae Kook Ha
  • Patent number: 12100784
    Abstract: A pixel includes a first bank pattern and a second bank pattern disposed on a base layer; a first electrode and a second electrode disposed on the first bank pattern and the second bank pattern, and spaced apart from each other; a light emitting element disposed between the first electrode and the second electrode, and including a first end electrically connected to the first electrode, and a second end electrically connected to the second electrode; and at least one insulating layer overlapping the light emitting element and at least one of the first electrode and the second electrode. The at least one insulating layer includes at least one of a first opening adjacent to the first end of the light emitting element and a second opening adjacent to the second end of the light emitting element.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: September 24, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hae Yun Choi, Jong Hyuk Kang, Hyun Deok Im, Jae Hoon Jung, Han Su Kim, Eun A Yang, Hyun Min Cho
  • Patent number: 9201114
    Abstract: A semiconductor integrated circuit includes at least one second semiconductor chip configured to generate an internal voltage, and a first semiconductor chip including a monitoring unit configured to monitor the internal voltage, and a first pad configured to provide monitoring result information outputted from the monitoring unit to a test device.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 1, 2015
    Assignee: SK Hynix Inc.
    Inventors: Sang-Mook Oh, Jae-Hyuk Im
  • Patent number: 8866521
    Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventors: Kang Seol Lee, Jae Hyuk Im
  • Patent number: 8803558
    Abstract: An integrated circuit includes a plurality of semiconductor devices. Each of the semiconductor devices includes an internal voltage generation unit configured to generate a plurality of internal voltages, a voltage select output unit configured to output a default voltage of a plurality of internal voltages to a preset pad in response to an initial value of a select code, and selectively output the other voltages of the plurality of internal voltages to the pad in response to variations of the select code, and a stack operation control unit configured to control the voltage select output unit to output the default voltage to the pad in response to a stack signal and a predetermined value of the select code, instead of the initial value of the select code, and whether or not to activate the stack signal is determined according to whether or not the plurality of semiconductor devices are stacked.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 12, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jae-Hyuk Im
  • Patent number: 8804447
    Abstract: A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: August 12, 2014
    Assignee: Conversant IP N.B. 868 Inc.
    Inventors: Jae-Hyuk Im, Woon-Bok Lee
  • Publication number: 20140133256
    Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.
    Type: Application
    Filed: January 17, 2014
    Publication date: May 15, 2014
    Applicant: SK hynix Inc.
    Inventors: Kang Seol LEE, Jae Hyuk IM
  • Patent number: 8724409
    Abstract: A semiconductor integrated circuit includes an internal reference voltage generation unit configured to generate an internal reference voltage; a high voltage generation unit configured to pump an external driving voltage based on the internal reference voltage applied from the internal reference voltage generation unit, and generate a high voltage having a specified level; and a reference voltage transfer unit configured to generate a test reference voltage from a reference voltage in a package test mode to correspond to a change in a driving operation of the external driving voltage applied from outside, and monitor and force the internal reference voltage.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: May 13, 2014
    Assignee: SK Hynix Inc.
    Inventors: Kang Seol Lee, Jae Hyuk Im
  • Publication number: 20140062534
    Abstract: An integrated circuit includes a plurality of semiconductor devices. Each of the semiconductor devices includes an internal voltage generation unit configured to generate a plurality of internal voltages, a voltage select output unit configured to output a default voltage of a plurality of internal voltages to a preset pad in response to an initial value of a select code, and selectively output the other voltages of the plurality of internal voltages to the pad in response to variations of the select code, and a stack operation control unit configured to control the voltage select output unit to output the default voltage to the pad in response to a stack signal and a predetermined value of the select code, instead of the initial value of the select code, and whether or not to activate the stack signal is determined according to whether or not the plurality of semiconductor devices are stacked.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 6, 2014
    Applicant: SK hynix Inc.
    Inventor: Jae-Hyuk IM
  • Patent number: 8659333
    Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.
    Type: Grant
    Filed: September 3, 2012
    Date of Patent: February 25, 2014
    Assignee: SK Hynix Inc.
    Inventors: Kang Seol Lee, Jae Hyuk Im
  • Patent number: 8638006
    Abstract: A semiconductor apparatus includes: a master chip and at least one slave chip configured to be stacked one on top of another; and a through-silicon via (TSV) configured to penetrate and electrically couple the master chip and the at least one slave chip, wherein the at least one slave chip receives a reference voltage generated from the master chip via the TSV and independently trims the reference voltage and then generates an internal voltage with the trimmed reference voltage.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: January 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jae Hyuk Im
  • Patent number: 8633742
    Abstract: A power-up signal generation circuit includes a power-up signal generator configured to enable a power-up signal when a level of an external power voltage is higher than a target level, and a target level controller configured to change the target level in response to a current consumption signal indicating a current consumption of a system including the power-up signal generation circuit.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: January 21, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Mook Oh, Jae-Hyuk Im
  • Publication number: 20140002120
    Abstract: A semiconductor integrated circuit includes at least one second semiconductor chip configured to generate an internal voltage, and a first semiconductor chip including a monitoring unit configured to monitor the internal voltage, and a first pad configured to provide monitoring result information outputted from the monitoring unit to a test device.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 2, 2014
    Inventors: Sang-Mook OH, Jae-Hyuk Im
  • Patent number: 8598943
    Abstract: A semiconductor integrated circuit includes a fuse set; a terminal assigned to be applied with a first external signal in a normal operation; and a control unit configured to receive a second external signal through the terminal and apply the received second external signal to the fuse set in a fuse control operation.
    Type: Grant
    Filed: August 27, 2011
    Date of Patent: December 3, 2013
    Assignee: SK Hynix Inc.
    Inventors: Sang Mook Oh, Jae Hyuk Im
  • Patent number: 8564138
    Abstract: A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: October 22, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kang-Seol Lee, Jae-Jin Lee, Jae-Hyuk Im
  • Publication number: 20130242679
    Abstract: A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.
    Type: Application
    Filed: May 13, 2013
    Publication date: September 19, 2013
    Applicant: 658868 N.B. Inc.
    Inventors: Jae-Hyuk IM, Woon-Bok LEE
  • Publication number: 20130234765
    Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.
    Type: Application
    Filed: September 3, 2012
    Publication date: September 12, 2013
    Applicant: SK HYNIX INC.
    Inventors: Kang Seol LEE, Jae Hyuk IM
  • Publication number: 20120267790
    Abstract: A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction.
    Type: Application
    Filed: August 2, 2011
    Publication date: October 25, 2012
    Inventors: Kang-Seol LEE, Jae-Jin LEE, Jae-Hyuk IM
  • Publication number: 20120249221
    Abstract: A semiconductor integrated circuit includes a fuse set; a terminal assigned to be applied with a first external signal in a normal operation; and a control unit configured to receive a second external signal through the terminal and apply the received second external signal to the fuse set in a fuse control operation.
    Type: Application
    Filed: August 27, 2011
    Publication date: October 4, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sang Mook OH, Jae Hyuk IM
  • Patent number: RE44218
    Abstract: A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 14, 2013
    Assignee: 658868 N.B. Inc.
    Inventors: Jae-Hyuk Im, Woon-Bok Lee