Abstract: There is an internal voltage generating circuit for providing a stable internal voltage by supplying the internal voltage before a time point when it is used. The internal voltage generating circuit includes a charge pump unit for generating an internal voltage lower than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.

Abstract: An internal voltage generator capable of reducing the variation width in the level of an internal voltage VPP, by performing charge pumping only a predetermined number of times in a period where an oscillator driving signal is at a logic HIGH level, and then stopping the charge pumping operation. The oscillator controller generates an oscillation control signal for stopping an oscillation operation of a ring oscillator by using an output signal of a level detector and an output signal of the ring oscillator. The ring oscillator does not generate an oscillation signal at a predetermined time point where an output signal of the level detector is at a HIGH level in response to the oscillation control signal. The charge pump circuit generates an internal voltage by performing a charge pumping operation only predetermined times in response to the oscillation signal, and then stopping the charge pumping operation.

Abstract: A redundancy circuit can include a first fuse set that is configured to receive an address signal and an initializing signal activated when power is up, and to output a first redundancy signal, the first redundancy signal being used to repair a defective cell by using a laser beam radiating method, a second fuse set that is configured to receive the initializing signal, a specific address signal, a test mode signal that is activated when a defective cell exists, and the address signal, and to output a second redundancy signal, the second redundancy signal being used to repair the defective cell by using an electrical fusing method, a first memory cell array that is controlled by the first redundancy signal, and a second memory cell array that is controlled by the second redundancy signal.

Abstract: An internal voltage generator of a semiconductor device consumes relatively small amount of driving current and generates a stable internal voltage with relatively small voltage level variation. The semiconductor device includes an oscillator configured to generate an oscillation signal in response to an input signal, wherein the oscillation signal oscillates with a first period and oscillates with a second period longer than the first period during a predetermined latter section, and an internal circuit configured to perform a predetermined operation in response to the oscillation signal.

Abstract: A bitline precharge voltage generator can generate multiple bitline precharge voltages when bitlines are precharged, thereby providing a stable operation regardless of a core voltage used as a high data voltage of a memory cell. In the bitline precharge voltage generator, a core voltage level detecting unit detects a core voltage level, activates a first enable signal when the core voltage level is lower than a specific voltage level, and activates a second enable signal when the core voltage level is higher than the specific voltage level. A bitline precharge voltage generating unit generates a bitline precharge voltage corresponding to half of the core voltage level when the first enable signal is activated. A bitline precharge voltage clamping unit generates a clamped bitline precharge voltage having a constant voltage level when the second enable signal is activated, regardless of the core voltage level.

Abstract: A semiconductor memory device includes a level feedback circuit and a refresh signal generator. The level feedback circuit outputs a bulk voltage applied to a cell transistor as a feedback signal. The refresh signal generator generates an internal refresh signal for driving a refresh operation at predetermined intervals during a self refresh mode. A period of the internal refresh signal is adjusted according to a voltage level of the feedback signal.

Abstract: A word line driving circuit and a semiconductor device using the same are disclosed. The word line driving circuit includes a second pad separated from a first pad, the first pad being applied with a first ground voltage, the second pad being applied with a second ground voltage, and a word line driver supplied with the second ground voltage, the word line driver driving word lines.

Abstract: A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than the external power. The level sensor senses a level of the internal voltage corresponding to a level of an adjusted reference voltage during a refresh mode. The oscillator generates a period signal in response to a sensing signal of the level sensor. The pumping control signal generator controls the operation of the charge pumping circuit in response to the period signal.

Abstract: A slew-rate adjusting apparatus for use in a semiconductor memory device includes: a slew-rate modulation signal generator for generating a slew-rate modulation signal according to the number of control codes having a first logic level among a plurality of control codes, which are programmable at an exterior; and a pre-driver for adjusting a slew rate of a data signal by changing the number of switching elements turned on in response to the slew-rate modulation signal.

Abstract: A method for controlling a precharge timing of a memory device is disclosed. The method includes making timing of generation of a signal for determining a precharge timing in a normal operation and a signal for determining a precharge timing in a refresh operation different from each other by making timing of generation of a signal for controlling the normal operation and a signal for controlling the refresh operation different from each other.

Abstract: A multi-port memory device includes a plurality of ports, a plurality of bank control units, a plurality of banks, a read clock generation unit, and a data transmission unit. Each of the banks is connected to a corresponding one of the bank control units. The read clock generation unit generates a read clock toggling for four clocks in response to a read command. The data transmission unit transmits a read data from the banks to a corresponding one of the ports in response to the read clock. Every bank control unit is connected to all of the ports.

Abstract: An internal voltage generator for stably generating an internal voltage includes a latch unit for outputting a first and a second driving signals based on a periodic signal; a first pump block for generating the internal voltage in response to the first driving signal; and a second pump block for generating the internal voltage in response to the second driving signal.

Abstract: A slew-rate adjusting apparatus for use in a semiconductor memory device includes: a slew-rate modulation signal generator for generating a slew-rate modulation signal according to the number of control codes having a first logic level among a plurality of control codes, which are programmable at an exterior; and a pre-driver for adjusting a slew rate of a data signal by changing the number of switching elements turned on in response to the slew-rate modulation signal.

Abstract: Provided is a memory device that can detect a mismatch in a bit line sense amp, wherein the memory device includes a sense amp drive unit for selectively supplying a pull-up drive voltage or a pull-down drive voltage to a bit line sense amp in response to a sensing test signal provided from outside.

Abstract: There is an internal voltage generating circuit for providing a stable internal voltage by supplying the internal voltage before a time point when it is used. The internal voltage generating circuit includes a charge pump unit for generating an internal voltage lower than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.

Abstract: A method for controlling a precharge timing of a memory device is disclosed. The method includes making timing of generation of a signal for determining a precharge timing in a normal operation and a signal for determining a precharge timing in a refresh operation different from each other by making timing of generation of a signal for controlling the normal operation and a signal for controlling the refresh operation different from each other.

Abstract: An internal voltage generator for stably generating an internal voltage includes a latch unit for outputting a first and a second driving signals based on a periodic signal; a first pump block for generating the internal voltage in response to the first driving signal; and a second pump block for generating the internal voltage in response to the second driving signal.

Abstract: Provided is an internal voltage generation circuit for generating an internal voltage used in a semiconductor device. The internal voltage generation circuit includes a standby internal voltage generator which is driven during a standby operation and an active operation and supplies a voltage to a core voltage end, a first active internal voltage generator for supplying a voltage to the core voltage end in response to an active signal activated during the active operation, and a second active internal voltage generator which is driven only for a predetermined time period in response to the active signal, and supplies a voltage to the core voltage end.

Abstract: There is an internal voltage generating circuit for providing a stable internal voltage by supplying the internal voltage before a time point when it is used. The internal voltage generating circuit includes a charge pump unit for generating an internal voltage lower than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.

Abstract: A multi-port memory device includes a first package ball out region in which a plurality of balls for a serial I/O interface part are arranged; and a second package ball out region in which a plurality of balls for a dynamic random access memory (DRAM) part are arranged.