Abstract: A multi-port memory device includes a plurality of ports, a plurality of bank control units, a plurality of banks, a read clock generation unit, and a data transmission unit. Each of the banks is connected to a corresponding one of the bank control units. The read clock generation unit generates a read clock toggling for four clocks in response to a read command. The data transmission unit transmits a read data from the banks to a corresponding one of the ports in response to the read clock. Every bank control unit is connected to all of the ports.

Abstract: The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval signal generator for providing a self-refresh interval signal notifying a self-refresh interval in response to the self-refresh entry signal and the self-refresh escape signal, a refresh cycle signal generator for periodically generating a cycle-pulse signal during an activation of the self-refresh interval signal, an internal refresh signal generator for producing an internal refresh signal in response to the self-refresh entry signal and the cycle-pulse signal, and an internal address counter for generating an internal address in response to the internal refresh signal.

Abstract: There is an internal voltage generating circuit for providing a stable high voltage by making a response time short. The internal voltage generating circuit includes a charge pump unit for generate a high voltage being higher than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.

Abstract: A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than the external power. The level sensor senses a level of the internal voltage corresponding to a level of an adjusted reference voltage during a refresh mode. The oscillator generates a period signal in response to a sensing signal of the level sensor. The pumping control signal generator controls the operation of the charge pumping circuit in response to the period signal.

Abstract: A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than the external power. The level sensor senses a level of the internal voltage corresponding to a level of an adjusted reference voltage during a refresh mode. The oscillator generates a period signal in response to a sensing signal of the level sensor. The pumping control signal generator controls the operation of the charge pumping circuit in response to the period signal.

Abstract: Provided is a technology for monitoring the electrical resistance of an element such as a fuse whose resistance is changed due to the electrical stress among internal circuits included in a semiconductor device. The present invention provides a monitoring circuit to monitor the change in the device specification during the device is being programmed and after the device is programmed. The present invention enables the verification of an optimized condition to let the device have a certain electrical resistance, by comparing the load voltage and the fuse voltage with the reference voltage that can sense the range of resistance variation more precisely. Also, it can guarantee device reliability since it is still possible to sense electrical resistance after the electrical stress is being given. Also, the present invention can increase the utility of the fuse by possessing an output to monitor electrical resistance sensed inside of the semiconductor.

Abstract: An internal voltage generator includes: an internal voltage driving unit for supplying an internal voltage corresponding to a reference voltage maintaining a predetermined voltage level regardless of a temperature variation; and a temperature compensation current sinking unit for sinking a current generated by an internal voltage in response to a voltage level inversely proportional to a temperature.

Abstract: The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval signal generator for providing a self-refresh interval signal notifying a self-refresh interval in response to the self-refresh entry signal and the self-refresh escape signal, a refresh cycle signal generator for periodically generating a cycle-pulse signal during an activation of the self-refresh interval signal, an internal refresh signal generator for producing an internal refresh signal in response to the self-refresh entry signal and the cycle-pulse signal, and an internal address counter for generating an internal address in response to the internal refresh signal.

Abstract: A multi-port memory device includes a plurality of ports located at a center region of the multi-port memory device, each for performing a data communication with a corresponding external device; a plurality of banks arranged at upper and lower regions of the multi-port memory device in a row direction on the basis of the plurality of ports; and first and second global I/O data buses arranged in the row direction between the banks and the ports, each for independently performing a data transmission between the banks and the ports.

Abstract: A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than the external power. The level sensor senses a level of the internal voltage corresponding to a level of an adjusted reference voltage during a refresh mode. The oscillator generates a period signal in response to a sensing signal of the level sensor. The pumping control signal generator controls the operation of the charge pumping circuit in response to the period signal.

Abstract: A word line driving circuit and a semiconductor device using the same are disclosed. The word line driving circuit includes a second pad separated from a first pad, the first pad being applied with a first ground voltage, the second pad being applied with a second ground voltage, and a word line driver supplied with the second ground voltage, the word line driver driving word lines.

Abstract: A slew-rate adjusting apparatus for use in a semiconductor memory device includes: a slew-rate modulation signal generator for generating a slew-rate modulation signal according to the number of control codes having a first logic level among a plurality of control codes, which are programmable at an exterior; and a pre-driver for adjusting a slew rate of a data signal by changing the number of switching elements turned on in response to the slew-rate modulation signal.

Abstract: Disclosed herein is an internal voltage generation circuit of a semiconductor memory device which is capable of supplying voltages of different levels to a column path & control logic and data path & control logic in the memory device according to different operation modes of the memory device. The column path & control logic and data path & control logic are applied with a normal operating voltage when they are involved in the current operation mode of the memory device, whereas with a lower voltage when they are not involved. Therefore, the present invention has the effect of efficiently managing internal voltages of the semiconductor memory device and reducing current leakage of the memory device and, in turn, unnecessary power consumption thereof.

Abstract: A redundancy circuit can include a first fuse set that is configured to receive an address signal and an initializing signal activated when power is up, and to output a first redundancy signal, the first redundancy signal being used to repair a defective cell by using a laser beam radiating method, a second fuse set that is configured to receive the initializing signal, a specific address signal, a test mode signal that is activated when a defective cell exists, and the address signal, and to output a second redundancy signal, the second redundancy signal being used to repair the defective cell by using an electrical fusing method, a first memory cell array that is controlled by the first redundancy signal, and a second memory cell array that is controlled by the second redundancy signal.

Abstract: Provided is an internal voltage generation circuit for generating an internal voltage used in a semiconductor device. The internal voltage generation circuit includes a standby internal voltage generator which is driven during a standby operation and an active operation and supplies a voltage to a core voltage end, a first active internal voltage generator for supplying a voltage to the core voltage end in response to an active signal activated during the active operation, and a second active internal voltage generator which is driven only for a predetermined time period in response to the active signal, and supplies a voltage to the core voltage end.

Abstract: A fuse monitoring circuit for a semiconductor memory device includes a fuse repair unit including a plurality of fuses each programmed with at least one repair address, configured to receive a fuse reset signal and to output a plurality of fuse state signals each corresponding to a connection state of one of the fuses, a fuse monitoring unit configured to receive a monitoring enable signal and to output a plurality of fuse state monitoring signals each corresponding to a corresponding one of the fuse state signals, each of the fuse state signals corresponding to one of a plurality of addresses, and an output unit configured to receive an output control signal and to output the fuse state monitoring signals to an output pad.

Abstract: A fuse monitoring circuit for a semiconductor device includes a repair fuse unit including a number of fuses to which a repair address is programmed, and configured to output fuse state signals corresponding to the connection states of the respective fuses in response to a fuse initialization signal. A serial fuse monitoring unit is configured to output a fuse state monitoring signal corresponding to each fuse state signal selected by an applied address in response to a serial monitoring test mode signal. Also, a parallel fuse monitoring unit is configured to output a repair monitoring signal by comparing an applied address and the repair address in response to a parallel monitoring test mode signal. An output unit is configured to output the fuse state monitoring signal and the repair monitoring signal to an output pad in response to an output control signal.

Abstract: Semiconductor device and data outputting method of the same includes an on die thermal sensor (ODTS) configured to output temperature information by detecting an internal temperature of the semiconductor device and an output driver configured to control a slew rate depending on the temperature information and output data.

Abstract: A test device that can improve test reliability is provided. In the test device, an error detecting unit detects an error of inputted test signals to generate an error flag, a normal test unit performs a test operation according to the test signals when the error flag is deactivated, and an error information providing unit indicates the error of the test signals when the error flag is activated.

Abstract: Provided are semiconductor design technologies, especially a bit line sense amplifier array of a semiconductor memory device. The semiconductor memory device includes a plurality of unit bit line sense amplifiers, a pull-up power line which is a power line of the plurality of unit bit line sense amplifiers, a single normal driver prepared on one side of the pull-up power line, and a plurality of over drivers arranged at regular intervals and partially connected to the pull-up power line.