Patents by Inventor Jae-Joon Kim

Jae-Joon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240107373
    Abstract: Provided is a communication method and an electronic device performing the communication method. The communication method includes establishing a wireless connection for transmission of data, generating a medium access control (MAC) frame including a header formed only of a frame control field based on a type of the data, and transmitting the MAC frame including the data.
    Type: Application
    Filed: August 7, 2023
    Publication date: March 28, 2024
    Inventors: Jae Sun CHA, Tae Joon PARK, Eun-Hee KIM, Kyeseon LEE
  • Patent number: 11942508
    Abstract: A display device includes a pixel in a display area. The pixel includes a first electrode and a second electrode that are spaced apart from each other, a first insulating layer disposed on the first and second electrodes and including a trench corresponding to a region between the first and second electrodes, light emitting elements disposed in the trench, each of the light emitting elements including a first end portion and a second end portion, a first contact electrode disposed on the first end portion of each of the light emitting elements and the first electrode, and a second contact electrode disposed on the second end portion of each of the light emitting elements and the second electrode. The trench includes a first trench accommodating the light emitting elements, and second trenches disposed in the first trench.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: March 26, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sung Hoon Kim, Yi Joon Ahn, Eun Kyung Yeon, Jae Been Lee
  • Patent number: 11942018
    Abstract: A display device is described including a display panel for displaying an image and an input sensing unit disposed on the display panel for sensing a user input. The input sensing unit includes: an electrode unit including first electrodes and second electrodes which intersect each other and a control unit for determining the proximity of an object or the shape of the object, based on capacitance change values of the first electrodes and the second electrodes. In a first mode the input sensing unit is driven using a self-capacitance method. The control unit may merge the capacitance change values, and determine the proximity of the object based on the merged value. In a second mode based on mutual capacitance, the control unit may determine the shape of the object.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: March 26, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae Woo Choi, Tae Joon Kim, Eun Sol Seo, Hyun Wook Cho
  • Publication number: 20240097425
    Abstract: A lightning rod with an electric double layer and electric dipole moment type discharge amplification function, the lightning rod including: a support member (100) for moving a lightning current to the ground; an emission member (200) fitted to the support member (100) to collect charges of the ground according to the approach of a thundercloud and thus emit a large number of ions with the opposite polarity to the polarity of the thundercloud; ground charge chargers (300) fitted to the support member (100) and having spaces formed therein to charge the charges of the ground; an insulation member (400) disposed on top of the emission member (200); and discharge induction members (500) fixedly disposed on top and underside of the emission member (200) by means of the insulation member (400).
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Dong-Jin KIM, Wan-Sung KWON, Sang-Won SEO, Yeong-Sin PARK, Sung-Joon LEE, Jae-Sang YOO
  • Patent number: 11927253
    Abstract: A powertrain for an electric vehicle includes: a planetary gear having a first rotating element, a second rotating element, and a third rotating element, wherein a first rotating element is connected to a first shaft and the second rotating element is connected to a second shaft; a first motor configured to selectively supply power to the first shaft at two or more gear ratios; a first shift assembly configured to transfer power of the first motor to the first shaft through one of two or more external engagement gear trains having different gear ratios; and a second motor configured to selectively supply power to the first shaft and the second shaft. The third shaft is fixedly disposed on a transmission housing, and any two shafts among the first, second and third shafts restrain each other.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: March 12, 2024
    Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventors: Jin Ho Kim, Jae Joon Lee, Jong Sool Park, Jin Young Hwang, Jong Sung Kim
  • Patent number: 11928578
    Abstract: A method of processing of a sparsity-aware neural processing unit includes receiving a plurality of input activations (IA); obtaining a weight having a non-zero value in each weight output channel; storing the weight and the IA in a memory, and obtaining an input channel index comprising a memory address location in which the weight and the IA are stored; and arranging the non-zero weight of each weight output channel according to a row size of an index matching unit (IMU) and matching the IA to the weight in the IMU comprising a buffer memory storing the input channel index.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: March 12, 2024
    Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION
    Inventors: Sungju Ryu, Jae-Joon Kim, Youngtaek Oh
  • Patent number: 11921139
    Abstract: A differential mode converter that includes an input mode converter configured to convert an input voltage in a single-ended mode into a first differential voltage and a second differential voltage to be output, the first differential voltage and the second differential voltage being symmetric with respect to a reference voltage and having a form of a square wave; and a chopper configured to receive the first differential voltage and the second differential voltage and determine a first chopping voltage and a second chopping voltage based on the first differential voltage and the second differential voltage to output the first chopping voltage and the second chopping voltage, the first chopping voltage and the second chopping voltage being symmetric with respect to the reference voltage and having a form of a DC voltage.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 5, 2024
    Assignee: ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jae Joon Kim, Seungmok Kim, Kyeong-Hwan Park
  • Patent number: 11920827
    Abstract: The present disclosure relates to an air cleaner. The air cleaner includes a main body, a panel configured to be movable with respect to the main body, a power transmission device connected to the panel, a vibration-preventing member connected to the power transmission device and including a vibration-preventing portion in contact with the power transmission device and a slip-preventing portion having a thickness thinner than the vibration-preventing portion, and a driving source connected to the vibration-preventing member.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mun Sub Kim, Jae-Woo Choi, Hyeong Joon Seo, Du Han Jung
  • Patent number: 11915859
    Abstract: Disclosed is a core for a current transformer, which forms an upper core in a round shape, and is disposed at a position lower than the center of a power line having both ends of the upper core received, thereby minimizing the stress of a magnetic path, and increases the permeability, thereby enhancing the magnetic induction efficiency. The disclosed core for the current transformer includes an upper core curved in a semi-circular shape to have a receiving groove formed therein, and having both ends extended downwards to be disposed to be spaced apart from each other and a lower core disposed on the lower portion of the upper core, and having both ends extended upwards to be disposed to face both ends of the upper core.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: February 27, 2024
    Assignee: AMOSENSE CO., LTD
    Inventors: Cheol-Seung Han, Won-San Na, Jin-Pyo Park, Young-Joon Kim, Jae-Jun Ko
  • Publication number: 20230362498
    Abstract: An electronic system may include: a camera to capture a current image; an image processor to generate current image data items; and a splitter circuit to generate first and second images having respective first and second image data items. The splitter circuit splits each current image data item into a first image data item with a first set of bits and a second image data item with a second set of bits distinct from the first set of bits. The first and second image data items correspond to two distinct precisions less than a precision of the current image data items. The electronic system may also include distinct binary neural network circuits to independently process the first and second images to generate first and second processed image data items; and a merger circuit to combine the processed image data items to recover output image data items for display.
    Type: Application
    Filed: July 17, 2023
    Publication date: November 9, 2023
    Applicant: Postech Research and Business Development Foundation
    Inventors: Hyungjun KIM, Yulhwa KIM, Sungju RYU, Jae-Joon KIM
  • Patent number: 11790985
    Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: October 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinseok Kim, Yulhwa Kim, Jae-Joon Kim, Hyungjun Kim
  • Patent number: 11755897
    Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.
    Type: Grant
    Filed: January 7, 2023
    Date of Patent: September 12, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Joon Kim, Hyungjun Kim, Yulhwa Kim
  • Publication number: 20230281436
    Abstract: A method for processing data based on a neural network including a first layer including axons and a second layer including neurons, includes receiving synaptic weights between the first layer and the second layer; generating presynaptic weights, a number of which is identical to a number of the axons, and postsynaptic weights, a number of which is identical to a number of the synaptic weights, from the synaptic weights; and storing the presynaptic weights and the postsynaptic weights in a synapse memory.
    Type: Application
    Filed: May 14, 2023
    Publication date: September 7, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Joon KIM, Jinseok KIM, Taesu KIM
  • Publication number: 20230260568
    Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 17, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinseok KIM, Yulhwa KIM, Jae-Joon KIM, Hyungjun KIM
  • Patent number: 11694067
    Abstract: An operating method of a neuromorphic processor which processes data based on a neural network including a first layer including axons and a second layer including neurons includes receiving synaptic weights between the first layer and the second layer, decomposing the synaptic weights into presynaptic weights, a number of which is identical to a number of the axons, and postsynaptic weights, a number of which is identical to a number of the synaptic weights, and storing the presynaptic weights and the postsynaptic weights. A precision of each of the synaptic weights is a first number of bits, a precision of each of the presynaptic weights is a second number of bits, and a precision of each of the postsynaptic weights is a third number of bits. The third number of the bits is smaller than the first number of the bits.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 4, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Joon Kim, Jinseok Kim, Taesu Kim
  • Patent number: 11681899
    Abstract: A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: June 20, 2023
    Assignees: Samsong Electronics Co., Ltd., POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Sungho Kim, Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim, Jinseok Kim
  • Publication number: 20230153594
    Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.
    Type: Application
    Filed: January 7, 2023
    Publication date: May 18, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Joon KIM, Hyungjun KIM, Yulhwa KIM
  • Patent number: 11651224
    Abstract: A method formats a weight matrix in a current layer included in a neural network. The method includes calculating a row length for each row of the weight matrix based on a number of elements each of which has non-zero value; storing rearrangement information including result of sorting rows in the order of row lengths; performing a row transformation or the row transformation and a column transformation on the weight matrix using the rearrangement information; distributing rows of a transformed weight matrix to a plurality of processing elements (PEs); and generating formatted data including one or more group data each including values and column information being processed in each of the PEs.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 16, 2023
    Assignees: SK hynix Inc., POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Junki Park, Jae-Joon Kim
  • Publication number: 20230131035
    Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 27, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungju RYU, Hyungjun KIM, Jae-Joon KIM
  • Publication number: 20230118943
    Abstract: A neuromorphic system includes an address translation device that translates an address corresponding to each of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address, and a plurality of synapse memories that store the synaptic weights based on the translation address. The translation address is generated such that at least two of synaptic weights corresponding to each of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories and such that at least two of synaptic weights corresponding to each of the presynaptic neurons are stored in different synapse memories.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Joon KIM, Jinseok KIM, Taesu KIM