Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: Disclosed is an electrical plant monitoring device which includes a plurality of flexible electrodes that are attached to a plate-shaped tissue and a tubular tissue of a plant, an impedance measurement unit that obtains electrical signals by using the plurality of flexible electrodes and measures impedance values associated with the plate-shaped tissue and the tubular tissue based on the electrical signals, and a spectrum monitor that generates an impedance spectrum based on the impedance values and monitors the impedance spectrum to sense an ion stress of the plant.

Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: A random access memory includes a first transistor including a first gate extending in a first direction, a second transistor including a second gate extending in a second direction perpendicular to the first direction and formed on an upper portion of the first transistor, and a storage node configured to connect a first gate of the first transistor to a drain of the second transistor and storing data.

Abstract: A random access memory includes a first transistor including a first gate extending in a first direction, a second transistor disposed on a same plane as the first transistor and including a second gate extending in the first direction, a third transistor including a third gate extending in a second direction perpendicular to the first direction and formed on the first transistor, a fourth transistor including a fourth gate extending in the second direction and formed on the second transistor, a first storage node connecting the first gate of the first transistor to a drain of the third transistor and storing data, and a second storage node connecting the second gate of the second transistor to a drain of the fourth transistor and storing data.

Abstract: A memory using ferroelectric metal field-effect transistors includes a drain, a source, and a gate formed on a substrate, a gate contact formed on an upper portion of the gate, and a ferroelectric layer disposed between the gate contact and the gate and configured to surround the gate contact, wherein the gate, the ferroelectric layer, and the gate contact operate as a capacitor having a metal-ferroelectric layer-metal (MFM) structure.

Abstract: A matrix data processing method performed by a computing device which performs a matrix multiplication operation includes, with respect to each of one or more elements included in a matrix, when a value of each element satisfies a designated condition, determining the element to be a don't-care element and determining an output value of the don't-care element, generating a bitstream based on the output value of the don't-care element and index values of valid elements included in the matrix, and equally dividing the bitstream into pieces of a designated number, and generating a Huffman code corresponding to each of a plurality of lower bitstreams that are generated as a result of the equal division.

Abstract: Disclosed is a mechanochromic array patch that implements, as a color change, a strain applied to a skin surface due to musculoskeletal movement. The mechanochromic array patch may include stretchable mechanochromic color-changing parts, a polymer connection part that connects the mechanochromic color-changing parts, and a water-insoluble support part. The polymer connection part may have a higher elastic modulus compared to the mechanochromic color-changing parts.

Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature 5 bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number 10 of digits of the addition result depending on a shift value to generate a shifted addition result and an accumulator generating output feature data based on the shifted addition result.

Abstract: Disclosed is a mechanochromic array patch that implements, as a color change, a strain applied to a skin surface due to musculoskeletal movement. The mechanochromic array patch may include stretchable mechanochromic color-changing parts, a polymer connection part that connects the mechanochromic color-changing parts, and a water-insoluble support part. The polymer connection part may have a higher elastic modulus compared to the mechanochromic color-changing parts.

Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.

Abstract: A method of processing of a sparsity-aware neural processing unit includes receiving a plurality of input activations (IA); obtaining a weight having a non-zero value in each weight output channel; storing the weight and the IA in a memory, and obtaining an input channel index comprising a memory address location in which the weight and the IA are stored; and arranging the non-zero weight of each weight output channel according to a row size of an index matching unit (IMU) and matching the IA to the weight in the IMU comprising a buffer memory storing the input channel index.

Abstract: A differential mode converter that includes an input mode converter configured to convert an input voltage in a single-ended mode into a first differential voltage and a second differential voltage to be output, the first differential voltage and the second differential voltage being symmetric with respect to a reference voltage and having a form of a square wave; and a chopper configured to receive the first differential voltage and the second differential voltage and determine a first chopping voltage and a second chopping voltage based on the first differential voltage and the second differential voltage to output the first chopping voltage and the second chopping voltage, the first chopping voltage and the second chopping voltage being symmetric with respect to the reference voltage and having a form of a DC voltage.

Abstract: An electronic system may include: a camera to capture a current image; an image processor to generate current image data items; and a splitter circuit to generate first and second images having respective first and second image data items. The splitter circuit splits each current image data item into a first image data item with a first set of bits and a second image data item with a second set of bits distinct from the first set of bits. The first and second image data items correspond to two distinct precisions less than a precision of the current image data items. The electronic system may also include distinct binary neural network circuits to independently process the first and second images to generate first and second processed image data items; and a merger circuit to combine the processed image data items to recover output image data items for display.

Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.

Abstract: A method for processing data based on a neural network including a first layer including axons and a second layer including neurons, includes receiving synaptic weights between the first layer and the second layer; generating presynaptic weights, a number of which is identical to a number of the axons, and postsynaptic weights, a number of which is identical to a number of the synaptic weights, from the synaptic weights; and storing the presynaptic weights and the postsynaptic weights in a synapse memory.

Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: An operating method of a neuromorphic processor which processes data based on a neural network including a first layer including axons and a second layer including neurons includes receiving synaptic weights between the first layer and the second layer, decomposing the synaptic weights into presynaptic weights, a number of which is identical to a number of the axons, and postsynaptic weights, a number of which is identical to a number of the synaptic weights, and storing the presynaptic weights and the postsynaptic weights. A precision of each of the synaptic weights is a first number of bits, a precision of each of the presynaptic weights is a second number of bits, and a precision of each of the postsynaptic weights is a third number of bits. The third number of the bits is smaller than the first number of the bits.

Abstract: A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.