Patents by Inventor Jae-Joon Kim

Jae-Joon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210303980
    Abstract: A method of processing of a sparsity-aware neural processing unit includes receiving a plurality of input activations (IA); obtaining a weight having a non-zero value in each weight output channel; storing the weight and the IA in a memory, and obtaining an input channel index comprising a memory address location in which the weight and the IA are stored; and arranging the non-zero weight of each weight output channel according to a row size of an index matching unit (IMU) and matching the IA to the weight in the IMU comprising a buffer memory storing the input channel index.
    Type: Application
    Filed: December 1, 2020
    Publication date: September 30, 2021
    Inventors: Sungju RYU, Jae-Joon KIM, Youngtaek OH
  • Patent number: 11091644
    Abstract: The present specification relates to a method for preparing a colorant composition comprising dissolving a first xanthene-based dye having the same number of positive charges and negative charges and a second xanthene-based dye having more negative charges than positive charges by one or more in a first solvent; and precipitating the dissolved first xanthene-based dye and the dissolved second xanthene-based dye in a second solvent, and a colorant composition, a colorant dispersion, a photosensitive resin composition, a color filter and a liquid crystal display device.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: August 17, 2021
    Assignee: LG CHEM, LTD.
    Inventors: Jongho Park, Dami Lee, Sanga Choi, Seung Jin Yang, Sang Gyun Park, Jae Joon Kim
  • Publication number: 20210209190
    Abstract: A matrix data processing method performed by a computing device which performs a matrix multiplication operation includes, with respect to each of one or more elements included in a matrix, when a value of each element satisfies a designated condition, determining the element to be a don't-care element and determining an output value of the don't-care element, generating a bitstream based on the output value of the don't-care element and index values of valid elements included in the matrix, and equally dividing the bitstream into pieces of a designated number, and generating a Huffman code corresponding to each of a plurality of lower bitstreams that are generated as a result of the equal division.
    Type: Application
    Filed: December 30, 2020
    Publication date: July 8, 2021
    Applicants: Daegu Gyeongbuk Institute Of Science And Technology, Postech Research And Business Development Foundation
    Inventors: Jaeha KUNG, Jae-Joon KIM, Junki PARK
  • Publication number: 20210132017
    Abstract: In a multi-channel resistance-based gas sensor system, the multi-channel array includes gas sensor channels respectively connected to resistive type gas sensors. The pre-processing unit selects one of a current mode, a resistance mode, and an external resistance mode, analyzes a sensing value obtained from any one of the gas sensor channels based on the selected mode and outputs a voltage value corresponding thereto. The ADC converts the voltage value to digital data. The control unit controls the pre-processing unit to execute one of the current mode for analyzing a sensing value smaller than or equal to a preset first resistance value, the external resistance mode for analyzing a sensing value greater than or equal to a preset second resistance value greater than the preset first resistance value and the resistance mode for analyzing a sensing value between the preset resistance first value and the preset second resistance value.
    Type: Application
    Filed: June 22, 2017
    Publication date: May 6, 2021
    Applicant: ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jae Joon KIM, Subin CHOI, Kyeong-Hwan PARK
  • Publication number: 20210074349
    Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
    Type: Application
    Filed: September 3, 2020
    Publication date: March 11, 2021
    Inventors: Jinseok KIM, Yulhwa KIM, Jae-Joon KIM, Hyungjun KIM
  • Publication number: 20210027142
    Abstract: Disclosed is a method of operating a neural network system. The method includes splitting input feature data into first splitting data corresponding to a first digit bit and second splitting data corresponding to a second digit bit different from the first digit bit, propagating the first splitting data through a first binary neural network, propagating the second splitting data through a second binary neural network, and merging first result data by propagation of the first splitting data and second result data by propagating the second splitting data to generate output feature data.
    Type: Application
    Filed: July 20, 2020
    Publication date: January 28, 2021
    Inventors: Hyungjun KIM, Yulhwa KIM, Sungju RYU, Jae-Joon KIM
  • Patent number: 10890633
    Abstract: There is provided a phase-domain detection apparatus for MIT application. The phase-domain detection apparatus includes a phase-locked loop unit configured to generate a plurality of reference clock signals having different phases and a phase-domain detection unit. The phase-domain detection unit is configured to receive the reference clock signals from the phase-locked loop unit, receive a response clock signal that is a phase-shifted reference clock signal of a reference clock signal inputted and passed through to a target object among the reference clock signals, and detect a phase difference between the reference clock signal inputted to the target object and the response clock signal.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: January 12, 2021
    Assignee: Ulsan National Institute of Science and Technology
    Inventors: Jae Joon Kim, Chansham Park
  • Publication number: 20200394504
    Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.
    Type: Application
    Filed: May 7, 2020
    Publication date: December 17, 2020
    Applicant: POSTECH Research and Business Development Foundation
    Inventors: Sungju RYU, Hyungjun KIM, Jae-Joon KIM
  • Publication number: 20200257753
    Abstract: A method for formatting a weight matrix including a plurality of sub matrices each being multiplied with an input vector may include sequentially adding weight information included in respective first columns of the plurality of sub matrices to formatted data; and sequentially adding weight information included in respective second columns of the plurality of sub matrices to the formatted data after the weight information from the first columns of the plurality of sub matrices. The weight information may be non-zero weight information.
    Type: Application
    Filed: January 21, 2020
    Publication date: August 13, 2020
    Applicants: SK hynix Inc., POSTECH ACADEMY-INDUSTRY FOUNDATION, POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Junki PARK, Jae-Joon KIM, Youngjae JIN, Euiseok KIM
  • Patent number: 10692935
    Abstract: Disclosed is a 3D static RAM core cell having a vertically stacked structure, including six thin-film transistors each having a gate electrode, a source electrode and a drain electrode, the static RAM core cell including two switching thin-film transistors, each connected to a bit line and a word line to select recording and reading of data, and four data-storage thin-film transistors connected to a power supply voltage (Vdd) or a ground voltage (Vss) to record and read data, the static RAM core cell including a first transistor layer including two thin-film transistors selected from among the six thin-film transistors, a second transistor layer disposed on the first transistor layer and including two thin-film transistors selected from among the remaining four thin-film transistors, and a third transistor layer disposed on the second transistor layer and including the remaining two thin-film transistors, at least one electrode of the first transistor layer and at least one electrode of the second transistor
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 23, 2020
    Assignees: CENTER FOR ADVANCED SOFT ELECTRONICS, POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Jimin Kwon, Sungjune Jung, Jae Joon Kim, Kilwon Cho, Sujeong Kyung
  • Publication number: 20200184315
    Abstract: A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.
    Type: Application
    Filed: September 5, 2019
    Publication date: June 11, 2020
    Applicants: Samsung Electronics Co., Ltd., POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Sungho KIM, Yulhwa KIM, Hyungjun KIM, Jae-Joon KIM, Jinseok KIM
  • Publication number: 20200166547
    Abstract: A resistance measuring device includes an amplifying unit including an amplifier, a first and a second current supply unit, a voltage detection unit, and a controller. The controller controls the voltage detection unit to detect a first output voltage of an output terminal of the amplifier in a state where the current of the first current source flows in a forward direction to a measurement target resistor by controlling the first current supply unit, controls the voltage detection unit to detect a second output voltage of the output terminal of the amplifier in a state where the current of the second current source flows in a reverse direction to the measurement target resistor by controlling the second current supply unit, and calculates a resistance value of the measurement target resistor based on the detected first output voltage and the detected second output voltage.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 28, 2020
    Applicant: Ulsan National Institute of Science and Technology
    Inventors: Jae Joon KIM, Subin CHOI
  • Publication number: 20200160160
    Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.
    Type: Application
    Filed: November 18, 2019
    Publication date: May 21, 2020
    Inventors: Jae-Joon KIM, Hyungjun KIM, Yulhwa KIM
  • Publication number: 20200052588
    Abstract: A differential mode converter that includes an input mode converter configured to convert an input voltage in a single-ended mode into a first differential voltage and a second differential voltage to be output, the first differential voltage and the second differential voltage being symmetric with respect to a reference voltage and having a form of a square wave; and a chopper configured to receive the first differential voltage and the second differential voltage and determine a first chopping voltage and a second chopping voltage based on the first differential voltage and the second differential voltage to output the first chopping voltage and the second chopping voltage, the first chopping voltage and the second chopping voltage being symmetric with respect to the reference voltage and having a form of a DC voltage.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Applicant: ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jae Joon KIM, Seungmok KIM, Kyeong-Hwan PARK
  • Publication number: 20200040188
    Abstract: The present specification relates to a method for preparing a colorant composition comprising dissolving a first xanthene-based dye having the same number of positive charges and negative charges and a second xanthene-based dye having more negative charges than positive charges by one or more in a first solvent; and precipitating the dissolved first xanthene-based dye and the dissolved second xanthene-based dye in a second solvent, and a colorant composition, a colorant dispersion, a photosensitive resin composition, a color filter and a liquid crystal display device.
    Type: Application
    Filed: June 5, 2018
    Publication date: February 6, 2020
    Applicant: LG CHEM, LTD.
    Inventors: Jongho PARK, Dami LEE, Sanga CHOI, Seung Jin YANG, Sang Gyun PARK, Jae Joon KIM
  • Publication number: 20200012925
    Abstract: A neuromorphic system includes an address translation device that translates an address corresponding to each of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address, and a plurality of synapse memories that store the synaptic weights based on the translation address. The translation address is generated such that at least two of synaptic weights corresponding to each of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories and such that at least two of synaptic weights corresponding to each of the presynaptic neurons are stored in different synapse memories.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 9, 2020
    Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: JAE-JOON KIM, Jinseok Kim, Taesu Kim
  • Patent number: 10524732
    Abstract: A composite monitoring apparatus includes a biosensor configured to sense a biometric signal of a driver in a motor vehicle, an air quality sensor configured to sense an air quality inside the motor vehicle, and a control unit. The control unit determines whether data on the air quality sensed by the air quality sensor exceeds an air quality reference value when data on the biometric signal sensed by the biosensor exceeds a biometric signal reference value. Further, the control unit generates an air quality warning alarm when the data on the air quality sensed by the air quality sensor exceeds the air quality reference value.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: January 7, 2020
    Assignee: UNIST (Ulsan National Institute of Science and Technology)
    Inventor: Jae Joon Kim
  • Publication number: 20200005126
    Abstract: An operating method of a neuromorphic processor which processes data based on a neural network including a first layer including axons and a second layer including neurons includes receiving synaptic weights between the first layer and the second layer, decomposing the synaptic weights into presynaptic weights, a number of which is identical to a number of the axons, and postsynaptic weights, a number of which is identical to a number of the synaptic weights, and storing the presynaptic weights and the postsynaptic weights. A precision of each of the synaptic weights is a first number of bits, a precision of each of the presynaptic weights is a second number of bits, and a precision of each of the postsynaptic weights is a third number of bits. The third number of the bits is smaller than the first number of the bits.
    Type: Application
    Filed: June 25, 2019
    Publication date: January 2, 2020
    Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Jae-Joon KIM, Jinseok KIM, Taesu KIM
  • Publication number: 20190392316
    Abstract: Provided are a weight matrix circuit and a weight matrix input circuit. The weight matrix circuit includes a memory array including n input lines, m output lines, and n×m resistive memory devices each connected to the n input lines and the m output lines and each having a non-linear current-voltage characteristic, an input circuit connected to each of the input lines, and an output circuit connected to each of the output lines. The input circuit is connected to the resistive memory devices such that the weight matrix circuit has a linear current-voltage characteristic.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 26, 2019
    Inventors: Jae-Joon KIM, Taesu KIM, Hyungjun KIM
  • Publication number: 20190347555
    Abstract: A method formats a weight matrix in a current layer included in a neural network. The method includes calculating a row length for each row of the weight matrix based on a number of elements each of which has non-zero value; storing rearrangement information including result of sorting rows in the order of row lengths; performing a row transformation or the row transformation and a column transformation on the weight matrix using the rearrangement information; distributing rows of a transformed weight matrix to a plurality of processing elements (PEs); and generating formatted data including one or more group data each including values and column information being processed in each of the PEs.
    Type: Application
    Filed: March 22, 2019
    Publication date: November 14, 2019
    Inventors: Junki PARK, Jae-Joon KIM