Abstract: Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

Abstract: A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug.

Abstract: Pulse generators include a delay circuit that is responsive to an input signal. The pulse generators also include an output circuit that is configured to generate an output pulse signal in response to the output of the delay circuit. In these pulse generators, the delay circuit has a variable delay that increases proportional to increases in a power supply voltage. Sense amplifiers that include these pulse generators are also provided.

Abstract: Provided are a program voltage generation circuit for achieving stable programming of a flash memory cell, and a method of programming a flash memory cell. In the program voltage generation circuit, a program wordline voltage to be applied to the gate of a flash memory cell is generated in response to a sink current provided by a constant current source and the result of a comparison between a reference voltage and a bitline voltage. The bitline voltage is generated according to a program current flowing to the first flash memory cell. A bitline current control voltage is generated in response to the program current that flows to a second flash memory cell in response to the program wordline voltage. Accordingly, even when the characteristics of the flash memory cell vary due to a change of a manufacturing process thereof, a constant program wordline voltage, a constant bitline voltage, and a constant bitline current control voltage are generated, and thus the flash memory cell is stably programmed.

Abstract: Provided are a program voltage generation circuit for achieving stable programming of a flash memory cell, and a method of programming a flash memory cell. In the program voltage generation circuit, a program wordline voltage to be applied to the gate of a flash memory cell is generated in response to a sink current provided by a constant current source and the result of a comparison between a reference voltage and a bitline voltage. The bitline voltage is generated according to a program current flowing to the first flash memory cell. A bitline current control voltage is generated in response to the program current that flows to a second flash memory cell in response to the program wordline voltage. Accordingly, even when the characteristics of the flash memory cell vary due to a change of a manufacturing process thereof, a constant program wordline voltage, a constant bitline voltage, and a constant bitline current control voltage are generated, and thus the flash memory cell is stably programmed.

Abstract: A novel method for forming contact holes is disclosed. According to the present invention, a silicon substrate is prevented from being over-etched by performing a two-step etching process. The first step is to etch a thick interlayer insulating layer until a thin etch stopper layer, formed beneath the interlayer insulating layer, is exposed. The second step is to over-etch the thin etch stopper layer. With this method, a lower capacitor electrode or a bit line can be prevented from being short-circuited with a well region of the silicon substrate, thereby reducing leakage currents.

Abstract: An integrated circuit field effect transistor includes contact pads which are separated by sidewall spacers. A first pad which electrically contacts one of the spaced-apart source and drain regions extends onto the gate electrode top, to define a first pad sidewall on the gate electrode top. A first capping layer on the first pad defines a first capping layer sidewall on the first pad. A first insulating sidewall spacer is formed on the first pad sidewall and on the first capping layer sidewall. A second pad, electrically contacting the other of the source and drain regions, extends onto the gate electrode top and contacts the first insulating sidewall spacer. A second capping layer may be formed on the second pad, opposite the substrate, to define a second capping layer sidewall on the first capping layer. A second insulating sidewall spacer may be formed on the second pad sidewall and on the second capping layer sidewall.

Abstract: There is disclosed a sector protecting circuit for a flash memory device. In order to prevent loss of data from a cell for sector protection, the sector protecting circuit for a flash memory device according to the present invention prevents loss of data by enabling a cell for sector protection to be erased or programmed along with a cell for normal sector.

Abstract: An integrated circuit field effect transistor includes contact pads which are separated by sidewall spacers. A first pad which electrically contacts one of the spaced-apart source and drain regions extends onto the gate electrode top, to define a first pad sidewall on the gate electrode top. A first capping layer on the first pad defines a first capping layer sidewall on the first pad. A first insulating sidewall spacer is formed on the first pad sidewall and on the first capping layer sidewall. A second pad, electrically contacting the other of the source and drain regions, extends onto the gate electrode top and contacts the first insulating sidewall spacer. A second capping layer may be formed on the second pad, opposite the substrate, to define a second capping layer sidewall on the first capping layer. A second insulating sidewall spacer may be formed on the second pad sidewall and on the second capping layer sidewall.

Abstract: A buried bit line DRAM cell and a manufacturing method thereof are provided. The buried bit line DRAM cell has a buried bit line formed into a trench which isolates devices, the buried bit line being isolated from a semiconductor substrate, a gate formed to be orthogonal to the bit line on the substrate, a first insulating layer formed to insulate the gate, a source and a drain of a transistor formed on the substrate at both sides of the gate, a self-aligned bit line contact formed between the first insulating layers for making contact between the drain and the buried bit line, and a self-aligned buried contact formed between the first insulating layers for making contact between the source and a storage electrode. According to the above structure, misalignment between the gate and the bit line and the excessive exposure to thermal processing which are inherent in conventional Buried Bit Line cells can be avoided and the design rule margin can be improved.

Abstract: The present invention relates to a flash memory device and more particularly to a flash memory device which can improve the performance of the memory cell due to the decrease in the verification time by performing the verification in parallel by selecting a plurality of addresses and then utilizing an integer multiple number of two or more of conventional verify modes at the time of verify mode.