Abstract: A method for forming a shallow well of a semiconductor device using low-energy ion implantation is provided. In one embodiment, a well region is formed to the depth of a trench isolation layer using a low-energy, high-dose ion implantation process.

Abstract: A semiconductor device for reducing junction leakage current and mitigating the narrow width effect, and a fabrication method thereof, are provided. The semiconductor device includes a semiconductor substrate in which an active region and an isolation region including a trench are formed, a spacer which is formed on both sidewalls of the trench, a channel stop impurity region which is self-aligned by the spacer and locally formed only at the lower portion of the isolation region, an isolation insulating layer in which the trench is buried, and a gate pattern which is formed on the isolation insulating layer and the active region. When the channel stop impurity region is formed only at the lower portion of the isolation region, isolation characteristics between unit cells can be improved, and also, a junction leakage current can be reduced.

Abstract: In a MOS transistor and a method of manufacturing the same, a gate structure including a gate insulating layer and a gate electrode is formed on a semiconductor substrate. A first insulating layer is formed to cover the gate structure. A second insulating layer is formed on the substrate that is spaced apart from the first insulating layer. A lightly doped source/drain region is formed in the surface portions of the substrate between the second insulating layer and the gate structure. A source/drain extension layer are formed on the lightly doped source/drain region. A heavily doped source/drain region is formed on the second insulating layer so as to connect with the source/drain extension layer. The short channel effect is suppressed and the source/drain junction capacitance is reduced.

Abstract: Methods of fabricating integrated circuit devices include forming a trench in a face of an integrated circuit substrate. The trench has a trench sidewall and a trench floor. The method further including forming a first insulating layer on the trench sidewall that exposes at least part of the trench floor and forming a conductive plug in the trench on the trench floor. The conductive plug is electrically connected to the substrate at the trench floor through the trench sidewall that exposes the at least part of the trench floor. The conductive plug also has a plug top opposite the trench floor that is recessed beneath the face of the substrate. The method further includes forming a second insulating layer on the plug top.

Abstract: Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region of the semiconductor substrate of a first conductivity type so that portions of the semiconductor substrate of a first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern. The MOS transistor also includes impurity regions having at least an upper surface of a second conductivity type disposed on the semiconductor substrate at at least one side of the insulated gate pattern, as well as at least one spacer disposed on at least one sidewall of the insulated gate pattern. The MOS transistor further contains a pad of a second conductivity type disposed on an upper surface of the impurity regions, whereby the pad covers a lower portion of the at least one spacer.

Abstract: The present invention provides novel cathecol hydrazone derivatives of formula (I) or pharmaceutically acceptable salts thereof, wherein R1 is C1-7 alkyl or C3-7 cycloalkyl; R2 is hydrogen, hydroxy, C1-5 alkyl or —CH2CH2C(═O)NH2; R3 and R4 are independently hydrogen, C1-7 alkyl, —C(═X)—R5, or 2-, 3- or 4-pyridyl, prymidyl or phenyl substituted with one or two selected from a group consisting of halogen, C1-6 alkoxy, nitro, trifluoromethyl, C1-6 alkyl and carboxyl, or R3 and R4 are directly bonded by C3-4 containing oxygen, sulfur or nitrogen to form a heterocyclic ring, X is oxygen, sulfur or NH and R5 is C1-7 alkyl, —NHR6, CONH2 or 2-, 3- or 4-pyridyl, prymidyl or phenyl substituted with one selected from a group consisting of halogen, C1-6 alkoxy, nitrile, trifluoromethyl, C1-6 alkyl and carboxyl, and R6 is hydrogen, hydroxy, NH2, C1-5 alkoxy, C1-5 alkyl, pyridyl or phenyl.

Abstract: Integrated circuit devices include an integrated circuit substrate having a face and a trench in the face. The trench has a trench sidewall and a trench floor. A first insulating layer is provided on the trench sidewall that exposes at least part of the trench floor and a conductive plug is provided in the trench on the trench floor. The conductive plug is electrically connected to the substrate at the trench floor through the trench sidewall that exposes the at least part of the trench floor. The conductive plug also has a plug top opposite the trench floor that is recessed beneath the face of the substrate. A second insulating layer is provided on the plug top. Methods of fabricating integrated circuit devices include forming a trench in a face of an integrated circuit substrate. The trench has a trench sidewall and a trench floor.

Abstract: A semiconductor device for reducing junction leakage current and mitigating the narrow width effect, and a fabrication method thereof, are provided. The semiconductor device includes a semiconductor substrate in which an active region and an isolation region including a trench are formed, a spacer which is formed on both sidewalls of the trench, a channel stop impurity region which is self-aligned by the spacer and locally formed only at the lower portion of the isolation region, an isolation insulating layer in which the trench is buried, and a gate pattern which is formed on the isolation insulating layer and the active region. When the channel stop impurity region is formed only at the lower portion of the isolation region, isolation characteristics between unit cells can be improved, and also, a junction leakage current can be reduced.

Abstract: A semiconductor device for reducing junction leakage current and mitigating the narrow width effect, and a fabrication method thereof, are provided. The semiconductor device includes a semiconductor substrate in which an active region and an isolation region including a trench are formed, a spacer which is formed on both sidewalls of the trench, a channel stop impurity region which is self-aligned by the spacer and locally formed only at the lower portion of the isolation region, an isolation insulating layer in which the trench is buried, and a gate pattern which is formed on the isolation insulating layer and the active region. When the channel stop impurity region is formed only at the lower portion of the isolation region, isolation characteristics between unit cells can be improved, and also, a junction leakage current can be reduced.

Abstract: Disclosed is a simple, economical and safe method of producing cellulose fibers with the use of a cold-pad-batch process. The method comprises adding alkali into fibers or fiber goods at least partially comprising cellulose diacetate fibers. In addition to exhibiting physical properties similar to those of viscose rayon fibers, the cellulose fibers are provided with an excellent sense of shari, which can be applied in cloth.

Abstract: Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region of the semiconductor substrate of a first conductivity type so that portions of the semiconductor substrate of a first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern. The MOS transistor also includes impurity regions having at least an upper surface of a second conductivity type disposed on the semiconductor substrate at at least one side of the insulated gate pattern, as well as at least one spacer disposed on at least one sidewall of the insulated gate pattern. The MOS transistor further contains a pad of a second conductivity type disposed on an upper surface of the impurity regions, whereby the pad covers a lower portion of the at least one spacer.

Abstract: Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region of the semiconductor substrate of a first conductivity type so that portions of the semiconductor substrate of a first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern. The MOS transistor also includes impurity regions having at least an upper surface of a second conductivity type disposed on the semiconductor substrate at at least one side of the insulated gate pattern, as well as at least one spacer disposed on at least one sidewall of the insulated gate pattern. The MOS transistor further contains a pad of a second conductivity type disposed on an upper surface of the impurity regions, whereby the pad covers a lower portion of the at least one spacer.

Abstract: Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region of the semiconductor substrate of a first conductivity type so that portions of the semiconductor substrate of a first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern. The MOS transistor also includes impurity regions having at least an upper surface of a second conductivity type disposed on the semiconductor substrate at at least one side of the insulated gate pattern, as well as at least one spacer disposed on at least one sidewall of the insulated gate pattern. The MOS transistor further contains a pad of a second conductivity type disposed on an upper surface of the impurity regions, whereby the pad covers a lower portion of the at least one spacer.

Abstract: Integrated circuit devices include an integrated circuit substrate having a face and a trench in the face. The trench has a trench sidewall and a trench floor. A first insulating layer is provided on the trench sidewall that exposes at least part of the trench floor and a conductive plug is provided in the trench on the trench floor. The conductive plug is electrically connected to the substrate at the trench floor through the trench sidewall that exposes the at least part of the trench floor. The conductive plug also has a plug top opposite the trench floor that is recessed beneath the face of the substrate. A second insulating layer is provided on the plug top. Methods of fabricating integrated circuit devices include forming a trench in a face of an integrated circuit substrate. The trench has a trench sidewall and a trench floor.

Abstract: A semiconductor device for reducing junction leakage current and mitigating the narrow width effect, and a fabrication method thereof, are provided. The semiconductor device includes a semiconductor substrate in which an active region and an isolation region including a trench are formed, a spacer which is formed on both sidewalls of the trench, a channel stop impurity region which is self-aligned by the spacer and locally formed only at the lower portion of the isolation region, an isolation insulating layer in which the trench is buried, and a gate pattern which is formed on the isolation insulating layer and the active region. When the channel stop impurity region is formed only at the lower portion of the isolation region, isolation characteristics between unit cells can be improved, and also, a junction leakage current can be reduced.

Abstract: A method for fabricating a semiconductor device with different gate oxide layers. Oxidation is controlled in accordance with the active area dimension so that oxide grows thin at a wider active width (peripheral region) and grows thickly at a narrower active width (cell array region). A gate pattern is formed on a semiconductor substrate having different active areas. Gate spacers are formed and then active dimension dependent oxidation process is performed to grow the oxide layers differently from one another.

Abstract: An apparatus for processing an order-wire signal capable of providing a high quality communication between operators through an order-wire channel for use in a synchronous add drop multiplexer(ADM) including a multiplexing unit and a de-multiplexing unit comprises: mixer for mixing two signals to generate a mixed signal, one being a voice signal of an operator at the ADM, the other being an order-wire signal received from a de-multiplexing unit in the ADM; detector for detecting a slip to generate a control signal and generating slip data; and selector for selecting one out of the mixed signal and the received order-wire signal to produce a selected signal, and transmitting the selected signal to the multiplexing unit in the ADM.

Abstract: A CRT comprising a front panel coated with a fluorescent layer on the inner surface thereof, a shadow mask, a mask frame separating the shadow mask at a distance from the front panel, a funnel extending outwardly from the front panel forming an envelope surrounded by the front panel and the funnel, and an inner shield inside such an envelope to shield against earth and other external magnetic fields. The mask frame and the inner shield are welded together at their ends.

Abstract: A video cassette recorder includes a driving unit, a pair of pole base assemblies and power conveying unit for conveying a power from the driving unit to the pole base assemblies, the power conveying unit having a pair of link devices for transmitting a power from the driving unit into its corresponding pole base assembly and allowing the pole base assemblies to load a tape. Each of the link devices has a deformable bent portion for exerting a resilient force on the loaded tape.

Abstract: A color cathode ray tube for permitting electron beams emitted from an electron gun to pass through apertures of a shadow mask and collide onto phosphors coated on the inner surface of a panel to thereby reproduce image information includes a magnetic shielding body which, for decreasing an influence of a terrestrial magnetic field, is formed of a rectangularly-shaped magnetic material and has one ends supported by the shadow mask to be symmetrical along the horizontal and vertical axes of the tube, and a plurality of notches formed into the magnetic shielding body are classified by the horizontal and vertical axes to be distributed asymmetrical with respect to the horizontal or vertical axes within four quadrants partitioned by the horizontal and vertical axes. Thus, the quantity of the landing variation in a specific portion having the greater quantity of the landing variation is reduced during the change of an outer magnetic field or the direction shift of the cathode ray tube.