Abstract: Disclosed herein is a method of printing a nanostructure including: preparing a template substrate on which a pattern is formed; forming a replica pattern having an inverse phase of the pattern by coating a polymer thin film on an upper portion of the template substrate, adhering a thermal release tape to an upper portion of the polymer thin film, and separating the polymer thin film from the template substrate; forming a nanostructure by depositing a functional material on the replica pattern; and printing the nanostructure deposited on the replica pattern to a substrate by positioning the nanostructure on the substrate, applying heat and pressure to the nanostructure, and weakening an adhesive force between the thermal release tape and the replica pattern by the heat.

Abstract: A color conversion substrate and a display device are provided. The color conversion substrate includes a base substrate, a first color filter and a second color filter disposed on a surface of the base substrate, a first partition layer disposed between the first color filter and the second color filter, a second partition layer disposed on the first partition layer, a first wavelength conversion pattern disposed on the first color filter and a second wavelength conversion pattern disposed on the second color filter, wherein the first partition layer includes a first lower surface disposed on the first color filter and a second lower surface disposed on the second color filter.

Abstract: A method of manufacturing a composite electrode for an all-solid-state battery includes: preparing a precursor solution by mixing at least one solid electrolyte precursor and at least one polar solvent; stirring the precursor solution; preparing an electrode slurry by adding an active material to the stirred precursor solution; and heat-treating the electrode slurry and obtaining the composite electrode for the all-solid-state battery, wherein the composite electrode for the all-solid-state battery includes: the active material; and a coating layer disposed on the active material and including a solid electrolyte.

Abstract: A light emitting diode including a side reflection layer. The light emitting diode includes: a semiconductor stack and a light exit surface having a roughened surface through which light generated from an active layer is emitted; side surfaces defining the light exit surface; and a side reflection layer covering at least part of the side surfaces. The light exit surface is disposed over a first conductivity type semiconductor layer opposite to the ohmic reflection layer, all layers from the active layer to the light exit surface are formed of gallium nitride-based semiconductors, and a distance from the active layer to the light exit surface is 50 ?m or more.

Abstract: The present disclosure relates to a method for carrying out dose delivery quality assurance for high-precision radiation treatment, in which parameters affecting a pass rate of dose delivery quality assurance can be derived through regression analysis, which is a known statistical analysis method, and a pass rate prediction model capable of predicting each parameter and the pass rate of dose delivery quality assurance can be derived, and accordingly, it can be predicted in advance whether dose delivery quality assurance will be passed according to the parameters through the above prediction model, without repeatedly carrying out dose delivery quality assurance according to a patient's treatment plan, and as a result, the efficiency of dose delivery quality assurance can be enhanced, and the time or capacity required for such quality assurance is reduced, such that radiation treatment for an actual patient can be quickly and precisely carried out.

Abstract: A low-noise amplifier in a receiver supporting a beam forming function may selectively change a phase shift for beam steering. The low-noise amplifier may include first and second transistors and a variable capacitance circuit connected to a gate of the second transistor. The variable capacitance circuit may selectively change capacitance thereof based on a capacitance control signal applied thereto according to beam-forming information, where the changed capacitance correspondingly causes a phase change in an output signal of the low-noise amplifier. A similar scheme may be employed for amplifiers in transmit signal paths to steer a transmit beam.

Abstract: A memory controller includes a plurality of processors, a memory device and a memory manager. The memory device includes a plurality of segments, which are divided into a plurality of segment groups, to which group identifiers are respectively assigned. The memory manager is configured to map a first buffer identifier to a first group identifier from among the group identifiers, select one or more segments only from a first segment group, to which the first group identifier is assigned among the plurality of segment groups, map the first buffer identifier to the one or more segments, and allocate, to a first processor from among the plurality of processors, the first buffer identifier and the one or more segments.

Abstract: Disclosed herein is a multi-cloud edge system. The multi-cloud edge system includes a core cloud, a multi-cluster-based first edge node system, and a multi-cluster-based near edge node system, wherein the multi-cluster-based first edge node system includes multiple worker nodes, and a master node including a scheduler.

Abstract: The present disclosure relates to technology for automatically searching and recovering the recovery area of frames corresponding to a desired time for large-capacity video evidence using a time map generated through an optical character recognition (OCR) function.

Abstract: A memory device includes a plurality of word lines and a plurality of bit lines intersecting the word lines, a memory cell array comprising a plurality of memory cells coupled between the word lines and the bit lines at intersections between the word lines and the bit lines, respectively, an address decoder suitable for decoding an address to access a memory cell selected among the memory cells, and a controller suitable for writing and reading data to and from the selected memory cell by applying voltages to the word lines and bit lines, wherein the controller invalidates data stored in memory cells coupled to a target word line among the word lines by applying an invalidation voltage to the target word line for a set time.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature in response to a first trimming signal as a default value and controlling the set period of the periodic signal based on the temperature in response to a second trimming signal, and an internal circuit to perform a set operation in response to the periodic signal.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: An internal control signal regulation circuit includes a programming test unit configured to detect an internal control signal in response to an external control signal and generate a selection signal, test codes and a programming enable signal; and a code processing unit configured to receive the test codes or programming codes in response to the selection signal and regulate the internal control signal.

Abstract: A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A semiconductor device includes a characteristic code storage unit configured to store signal transfer characteristic information input through a given pad and output a control code corresponding to the signal transfer characteristic information, and a characteristic reflection unit configured to reflect the signal transfer characteristic information in an input signal input through the given pad, in response to the control code, and to output the reflected input signal.