Abstract: A semiconductor package includes a bonding wire which is connected to a semiconductor chip. A first encapsulation layer which surrounds the bonding wire is disposed. A second encapsulation layer which surrounds the first encapsulation layer is disposed. A surface roughness of the first encapsulation layer is less than that of the second encapsulation layer. A landing pad which contacts the bonding wire is disposed.

Abstract: The armrest assembly includes a locking device for restricting an armrest when the armrest assumes a locking posture, thereby limiting rotation of the armrest. The locking device includes a lock shaft fixed on the center of rotation of the armrest and a lock provided at the armrest SO as to be movable in a locking direction approaching the lock shaft and an unlocking direction away from the lock shaft in accordance with operation of the knob. A locking section including a recess into which a lock tooth is inserted when the armrest is in the locking posture and an unlocking section extending from the locking section are formed along the periphery of the lock shaft, and the unlocking section includes an unlocking surface that contacts a tooth end to maintain the lock in the state of being moved in the unlocking direction.

Abstract: The locking device includes a cam member rotatable about a second axis parallel to a first axis and a rotator for transmitting rotational force of an armrest to the cam member in a contact manner to control rotation of the cam member. When the armrest is rotated, the rotator is rotated about the first axis, and a locking tooth of the rotator is moved so as to pass through a locking position. The cam member is rotated in accordance with control operation of rotation of the rotator, and a locking recess in the cam member is moved so as to pass through the locking position. When the armrest is rotated to assume a locking posture, the locking tooth and the locking recess are moved to the locking position, and the locking tooth is inserted into the locking recess.

Abstract: Disclosed is a method of forming an area-selective thin film, the method comprising supplying a nuclear growth retardant to the inside of the chamber in which the substrate is placed, so that the nuclear growth retardant is adsorbed to a non-growth region of the substrate; purging the interior of the chamber; supplying a precursor to the inside of the chamber, so that the precursor is adsorbed to a growth region of the substrate; purging the interior of the chamber; and supplying a reaction material to the inside of the chamber, so that the reaction material reacts with the adsorbed precursor to form the thin film.

Abstract: According to one embodiment of the present invention, a method for forming a thin film using a surface protection material comprises: a surface protection layer forming step of forming a surface protection layer on the surface of a substrate by supplying a surface protection material to the inside of a chamber in which the substrate is placed; a step of performing a primary purging of the inside of the chamber; a metal precursor supply step of supplying a metal precursor to the inside of the chamber; a step of performing a secondary purging of the inside of the chamber; and a thin film forming step of supplying a reactive material to the inside of the chamber so as to react with the metal precursor and form a thin film.

Abstract: A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

Abstract: A multi-view service providing method according to an embodiment of the present invention is performed through an apparatus including a processor and a memory, and the method comprises the steps of: (a) receiving one or more videos from one or more cameras individually capturing each artist belonging to an artist group; (b) determining a multi-view layout setting on a user's terminal for the received one or more videos; and (c) outputting the received one or more videos on the user's terminal according to the determined multi-view layout setting by the one or more processors in combination with a computing device, and the multi-view layout setting includes a first multi-view layout setting including one main video and one or more sub-videos on one screen, and a second multi-view layout setting including one or more main videos on one screen.

Abstract: Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.

Abstract: A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.

Abstract: A light emitting display device in which odd scan stages receive odd first and second scan clocks alternately, and even scan stages receive an even scan clock, in a multi-frequency mode in which a first region is driven at a higher frequency than a second region, an odd first scan clock is provided to a n+5-th scan stage at a begin of the second region, an even scan clock is provided to a n+4-th scan stage at an end of the first region, and an odd second scan clock is provided to a n+3-th scan stage of the first region, and in the multi-frequency mode, during a driving frame of refreshing the first region and refresh-skipping the second region, the odd first scan clock does not have an i+2-th clock pulse corresponding to a scan pulse of the n+4-th first scan line.

Abstract: The technology is generally directed to providing information associated with a digital component via a visual code after confirming the user scanning the visual code is authorized to access the information. The visual code may be provided for output within or near a digital component on a display device. When the visual code is scanned by an image capturing device, account data associated with the digital component may be compared to profile data of a user profile that is logged into the image capturing device. When the account data corresponds to the profile data, the data associated with the digital component may be provided for display on the image capturing device. When the account data does not correspond to the profile information, a prompt may be provided.

Abstract: Disclosed are a substrate processing equipment and a method of driving the substrate processing equipment, which automatically cut off power supplied to a main circuit breaker and a branch circuit breaker when an operator inspects a process chamber or a power supply system. The substrate processing equipment for processing a substrate includes: a process processing module including loads utilized in a process for processing a substrate; a branch circuit breaker installed on a periphery to the process processing module and electrically connected to the loads; a main circuit breaker electrically connected to the branch circuit breaker and supplying power to the branch circuit breaker; and a power distribution board in which the branch circuit breaker is mounted, and including a power distribution board door, in which the main circuit breaker cuts off power when the power distribution board door is opened.

Abstract: The present invention relates to a polyamide resin composition and a molded article formed from same, the polyamide resin composition comprising: polyamide 6; long-chain polyamide; an impact modifier; and polyamide 66, aromatic polyamide, and a combination thereof.

Abstract: Disclosed is a method for removing nitrogen and phosphorus from sewage and wastewater through a combination of a biological nitrogen and phosphorus removal process using nitrite nitrogen and an anaerobic ammonium oxidation process. An objective of an embodiment of the present invention is to provide an apparatus for removing nitrogen and phosphorus in which, by inducing a denitritation- and nitritation-based biological nitrogen and phosphorus removal process in a bioreactor and applying an anaerobic ammonium oxidation process, nitrogen and phosphorus can be economically and effectively removed without separately injecting organic materials.

Abstract: A battery module includes: a battery cell having a cell vent; and a bus bar holder on the battery cell and having a module vent. The module vent having a flat first surface, a flat second surface opposite to the first surface and facing the battery cell, a vent hole extending between the first and second surfaces and facing the cell vent, and a plurality of bending guide grooves in a partial region of the first surface spaced apart from the vent hole.

Abstract: Systems and methods are described for integrated decomposition and scanning of a semiconducting wafer, where a single chamber is utilized for decomposition and scanning of the wafer of interest.

Abstract: A light emitting display device in which odd scan stages receive odd first and second scan clocks alternately, and even scan stages receive an even scan clock, in a multi-frequency mode in which a first region is driven at a higher frequency than a second region, an odd first scan clock is provided to a n+5-th scan stage at a begin of the second region, an even scan clock is provided to a n+4-th scan stage at an end of the first region, and an odd second scan clock is provided to a n+3-th scan stage of the first region, and in the multi-frequency mode, during a driving frame of refreshing the first region and refresh-skipping the second region, the odd first scan clock does not have an i+2-th clock pulse corresponding to a scan pulse of the n+4-th first scan line.

Abstract: Disclosed is a method of forming a thin film using a chemical purge material, the method comprising supplying a metal precursor to the inside of a chamber oh which a substrate is placed; purging the interior of the chamber; supplying a reactant to the inside of the chamber so that the reactant reacts with the metal precursor to form the thin film; and supplying a chemical purge material to the inside of the chamber so that a portion of the reactant is removed.