Abstract: The present invention relates to a method for fabricating a capacitor in a semiconductor device through the use of hafnium-terbium oxide (Hf1-xTbxO) as a dielectric layer. The method includes the steps of: forming a lower electrode on a substrate; forming an amorphous hafnium-terbium oxide (Hf1-xTbxO) dielectric layer on the lower electrode; crystallizing the Hf1-xTbxO dielectric layer by performing a thermal process; and forming an upper electrode on the Hf1-xTbxO dielectric layer.

Abstract: The present invention relates to a dielectric layer alloyed with hafnium oxide and aluminum oxide and a method for fabricating the same. At this time, the dielectric layer is deposited by an atomic layer deposition technique. The method for fabricating the hafnium oxide and aluminum oxide alloyed dielectric layer includes the steps of: depositing a single atomic layer of hafnium oxide by repeatedly performing a first cycle of an atomic layer deposition technique; depositing a single atomic layer of aluminum oxide by repeatedly performing a second cycle of the atomic layer deposition technique; and depositing a dielectric layer alloyed with the single atomic layer of hafnium oxide and the single atomic layer of aluminum oxide by repeatedly performing a third cycle including the admixed first and second cycles.

Abstract: The present invention relates to a capacitor having a hafnium oxide and aluminum oxide alloyed dielectric layer and a method for fabricating the same. The capacitor includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer, wherein a portion of the dielectric layer contacting one of the lower electrode and the upper electrode is formed by alloying hafnium oxide and aluminum oxide together.

Abstract: A capacitor using a high dielectric constant film for a semiconductor memory device, and a fabrication method thereof are provided that improve a process margin and achieve a stable contact. The capacitor can be fabricated by forming an impurity layer at a surface of a semiconductor substrate, forming an interlayer insulation film on the semiconductor substrate having a contact hole filled with a conductive material coupled to the impurity layer, and sequentially forming a first oxide film, a nitride film and a second oxide film on the interlayer insulation film so that the contact hole is exposed therethrough, and the nitride film and the first oxide film are partially exposed through the second oxide film. A diffusion barrier film is formed at outer and side portions of the second oxide film, outer and side portions of the nitride film, side portions of the first oxide film, and on an exposed portion of the contact hole.

Abstract: A capacitor using a high dielectric constant film for a semiconductor memory device, and a fabrication method thereof are provided that improve a process margin and achieve a stable contact. The capacitor can be fabricated by forming an impurity layer at a surface of a semiconductor substrate, forming an interlayer insulation film on the semiconductor substrate having a contact hole filled with a conductive material coupled to the impurity layer, and sequentially forming a first oxide film, a nitride film and a second oxide film on the interlayer insulation film so that the contact hole is exposed therethrough, and the nitride film and the first oxide film are partially exposed through the second oxide film. A diffusion barrier film is formed at outer and side portions of the second oxide film, outer and side portions of the nitride film, side portions of the first oxide film, and on an exposed portion of the contact hole.

Abstract: A capacitor using a high dielectric constant film for a semiconductor memory device, and a fabrication method thereof are provided that improve a process margin and achieve a stable contact. The capacitor can be fabricated by forming an impurity layer at a surface of a semiconductor substrate, forming an interlayer insulation film on the semiconductor substrate having a contact hole filled with a conductive material coupled to the impurity layer, and sequentially forming a first oxide film, a nitride film and a second oxide film on the interlayer insulation film so that the contact hole is exposed therethrough, and the nitride film and the first oxide film are partially exposed through the second oxide film. A diffusion barrier film is formed at outer and side portions of the second oxide film, outer and side portions of the nitride film, side portions of the first oxide film, and on an exposed portion of the contact hole.

Abstract: Methods of forming a MOS transistor having dual gates minimizes impurity channeling and diffusion that can occur during impurity injection and activating processes. A method of fabricating the transistor includes the steps of forming a first conduction type well and a second conduction type well in a semiconductor substrate having an isolation region and an active region formed therein. Then, a gate oxide film is formed on an entire surface of the substrate, and a polysilicon layer is deposited on the gate oxide film preferably at a temperature of about 660° C. to about 700° C. and a pressure of about 10 to about 300 Torr. Next, portions of the polysilicon layer and the gate oxide film are selectively removed to form a gate electrode on each of the wells. Impurity ions are injected, having a conduction type opposite a conduction type of the corresponding well, into an exposed surface of each of the wells, to form lightly doped impurity regions.

Abstract: A method for fabricating a contact pad for a semiconductor device, including the steps of forming device isolation layers in a semiconductor substrate to define active regions, forming a plurality of wordlines crossing the active regions, forming an insulating layer on an entire surface, and selectively removing the insulating layer on storage node contact regions, a bitline contact region, and the device isolation layer in contact with the bitline contact region, so as to form an epitaxial growth blocking layer, and conducting an epitaxial growth using the epitaxial growth blocking layer as a mask, to form a storage node contact pad as well as a bitline contact pad by causing an epitaxial layer grown in the bitline contact region to extend laterally toward the device isolation layer.

Abstract: A semiconductor device and a method for manufacturing the same that forms a self-aligned contact hole between two gate lines. A substrate is provided that has a first gate line formed thereon. An insulator is formed on the first gate line and substrate. Then a portion of the insulator and a portion of the first gate line is selectively removed to split the first gate line into a second gate line and a third gate line and to concurrently expose the substrate. Thus, producing a self-aligned contact hole between the second and third gate lines.

Abstract: A semiconductor memory device suitable for forming a capacitor using a high dielectric film for a highly integrated semiconductor device includes a semiconductor substrate, an insulating film having a contact hole, the insulating film being over the semiconductor substrate, a conductive film on the semiconductor substrate through the contact hole, the conductive film having a top portion acting as a diffusion barrier, a first electrode over the conductive films, a dielectric film over the first electrode, and a second electrode over the dielectric film.

Abstract: A semiconductor device and a method for manufacturing the same that forms a self-aligned contact hole between two gate lines. A substrate is provided that has a first gate line formed thereon. An insulator is formed on the first gate line and substrate. Then a portion of the insulator and a portion of the first gate line is selectively removed to split the first gate line into a second gate line and a third gate line and to concurrently expose the substrate. Thus, producing a self-aligned contact hole between the second and third gate lines.

Abstract: A semiconductor memory device suitable for forming a capacitor using a high dielectric film for a highly integrated semiconductor device includes a semiconductor substrate, an insulating film having a contact hole, the insulating film being over the semiconductor substrate, a conductive film on the semiconductor substrate through the contact hole, the conductive film having a top portion acting as a diffusion barrier, a first electrode over the conductive films, a dielectric film over the first electrode, and a second electrode over the dielectric film.

Abstract: The present invention provides a method of forming a high strength dielectric film which provides a high dielectric constant for a high density device, and a method of fabricating a capacitor using such a method. The method includes a two step process where one of the steps provides a composition BST layer serving as a nucleation layer. For example, a BST layer having a composition of Ba.sub.x Sr.sub.1-x TiO.sub.3, where X has a range of about 0 to 0.4. Another BST layer having a composition of Ba.sub.x Sr.sub.1-x TiO.sub.3 is provided, where X is about 0.5. Such a method provides a high dielectric film with a very smooth surface, compared to conventional methods.

Abstract: A crystallization process comprising the steps of depositing a polycrystalline silicon layer on a semiconductor substrate, implanting silicon ions into first and second areas of the polycrystalline silicon layer in different amounts such that crystals having a predetermined plane direction remain in the second area and such that the first area becomes amorphous, and performing a thermal treatment to recrystallize the amorphous second area using the crystals having the predetermined plane direction remaining in the first area as a nucleus.

Abstract: A method for making semiconductor thin film transistors (TFTs) having a bottom gate such that the gate electrode is formed in a furrow of an insulating layer, with a gate oxide and body polysilicon formed thereon, thereby allowing the source and drain level to be in a smooth plane parallel with the gate level. Steps that may be included in the disclosed method for fabricating thin film transistors having a bottom gate are: a) forming an insulating layer on a substrate, and forming a furrow by etching the insulating layer at a portion corresponding to where a gate line is to be formed; b) forming a gate line in the furrow by depositing a conductive layer, and etching back the conductive layer; c) forming a gate insulator on the gate line, forming a semiconductor layer on the gate insulator; and d) forming impurity regions at opposite sides of the gate line.

Abstract: The capacitor area is increased with a cylinder-shaped first storage electrode overlapped with a second electrode in an area which covers two adjacent cells. Included in a semiconductor device using the invention may be: a semiconductor substrate; a word line on the substrate; impurity regions at opposite sides of the word line in the substrate; a first contact hole on an odd impurity region; a first storage electrode connected to the first contact hole, which is overlapped with an adjacent even cell; a first sidewall storage electrode at opposite sides of the first storage electrode; a second contact hole on the even impurity region, the second contact hole having an insulated sidewall; a second storage electrode connected to the second contact hole, which is overlapped with an adjacent odd cell; a second sidewall storage electrode at opposite sides of the second storage electrode.

Abstract: A method for forming a capacitor of a memory cell is disclosed. Steps of the present invention may include: forming a first conductive layer on a substrate; forming a tantalum oxide layer on the first conductive layer; forming a silicon nitride layer on the tantalum oxide layer; carrying out a titanium ion implantation into the tantalum oxide layer; carrying out a heat treatment, which may form a silicon oxide layer between the first conductive layer and the tantalum oxide layer, and which may include titanium oxide in the tantalum oxide layer, and which may change the silicon nitride to an oxynitride layer; and forming a second conductive layer on the oxynitride layer. During the titanium ion implantation process, Ti(OCH.sub.3).sub.4 may be used as a titanium ion source. The titanium ion implantation process may be carried out using the Si.sub.3 N.sub.4 layer as a buffer layer, and with an energy of about 5 KeV-15 KeV, and a dosage of about 10.sup.13 -10.sup.16.

Abstract: The capacitor area is increased with a cylinder-shaped first storage electrode overlapped with a second electrode in an area which covers two adjacent cells. Included in a semiconductor device using the invention may be: a semiconductor substrate; a word line on the substrate; impurity regions at opposite sides of the word line in the substrate; a first contact hole on an odd impurity region; a first storage electrode connected to the first contact hole, which is overlapped with an adjacent even cell; a first sidewall storage electrode at opposite sides of the fist storage electrode; a second contact hole on the even impurity region, the second contact hole having a insulated sidewall; a second storage electrode connected to the second contact hole, which is overlapped with an adjacent odd cell; a second sidewall storage electrode at opposite sides of the second storage electrode.