Abstract: An apparatus for generating a roll map of a merge-wound electrode includes a position measurement device configured to acquire coordinate value data for a longitudinal position of an electrode according to an amount of rotation of the rewinder. The apparatus includes an input device configured to input an input signal indicating a start of merge-winding or an end of merge-winding, a seam detector configured to detect a seam, a reference point detector configured to detect a plurality of reference points of the merge-wound electrode, and a roll map generator configured to generate a roll map for simulating the merge-wound electrode moving in a roll-to-roll state based on the input signal of the input device, and to display the longitudinal coordinate values of the electrode, the electrode coordinate values of the seam, and the electrode coordinate values of the plurality of reference points of the merge-wound electrode on the roll map.

Abstract: A cathode for a lithium secondary battery includes a cathode current collector, and a cathode active material layer formed on the cathode current collector. The cathode active material layer includes a cathode active material and a conductive material ID/IG is in a range from 0.5 to 1.25 in a Raman spectrum of the cathode active material layer. The cathode active material includes lithium metal oxide particles containing nickel and manganese and having a content of cobalt of less than 2 mol % among all elements except for lithium and oxygen.

Abstract: A refrigerator has a shelf seating protrusion and a separate shelf seating member. The shelf seating protrusion is not formed at an approximate mid-point, height wise, of a storage space defined by an inner casing. The shelf seating member may be coupled to the inner casing to support a shelf assembly. An arrangement of the shelf seating protrusions and the shelf seating member is configured to reduce deformation and cracking of the inner casing due to thermal impact in a manufacturing process or when items are stored on the shelf assembly.

Abstract: A binder solution for an all-solid-state battery, an electrode slurry for an all-solid-state battery including the same and a method of manufacturing an all-solid-state battery using the same, and more particularly to a binder solution for an all-solid-state battery, in which a polymer binder configured such that a non-polar functional group is bonded to the end of a polar functional group is used, whereby the polar functional group is provided by a deprotection mechanism of the polymer binder through a thermal treatment, thus increasing adhesion between electrode materials to thereby improve battery capacity and enabling a wet process to thereby reduce manufacturing costs, an electrode slurry for an all-solid-state battery including the same and a method of manufacturing an all-solid-state battery using the same.

Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.

Abstract: A touch sensor includes first touch cells disposed in a first touch sensing area, the first touch cells each including a first touch pattern and a first dummy pattern, and second touch cells disposed in a second touch sensing area, the second touch cells each including a second touch pattern and a second dummy pattern. An area of a first dummy pattern area in which the first dummy pattern is disposed is greater than an area of a second dummy pattern area in which the second dummy pattern is disposed.

Abstract: A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.

Abstract: A display apparatus includes a base substrate, a light emitting structure disposed on the base substrate, and a thin film encapsulation layer disposed on the light emitting structure and including at least one inorganic layer and at least one organic layer. The at least one inorganic layer includes a high density layer having a density of greater than or equal to about 2.0 g/cm3 and a low density layer having a density of less than about 2.0 g/cm3. The high density layer and the low density layer are in contact with each other.

Abstract: A display device includes a substrate that includes a display area and a non-display area, a display element layer disposed on the display area of the substrate, an opposing substrate that faces the substrate and the display element layer, a sealing member disposed on the non-display area and that couples the substrate and the opposing substrate, and a filler disposed between the substrate and the opposing substrate. A thickness of the filler varies in the range of 60% to 400% of a thickness of the sealing member.

Abstract: Methods and systems for executing tracking and monitoring manufacturing data of a battery are disclosed. One method includes: receiving, by a server system, sensing data of the battery from a sensing system; generating, by the server system, mapping data based on the sensing data; generating, by the server system, identification data of the battery based on the sensing data; generating, by the server system, monitoring data of the battery based on the sensing data, the identification data, and the mapping data; and generating, by the server system, display data for displaying a simulated electrode of the battery on a graphical user interface based on the monitoring data of the battery.

Abstract: As one aspect of the present disclosure, an electronic device is disclosed. The device may include: a volatile memory device; and a controller configured to be connected with a host processor and the volatile memory device, wherein the controller may be further configured to receive a request related to data access from the host processor, determine whether data corresponding to address information is compressed based on the address information included in the request, and communicate with the volatile memory device and process the request based on a result of determining whether the data is compressed.

Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.

Abstract: A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.

Abstract: A display device includes: a display panel including a display area including pixels and a non-display area including a dummy pixel; a scan driver which supplies a scan signal to the display panel; a data driver which supplies a data signal to the display panel; and a timing controller which supplies a first control signal for controlling the scan driver and a second control signal for controlling the data driver. The dummy pixel is connected to a bad pixel among the pixels in the display area through a repair line, and a connection of the dummy pixel to the repair line is cut off in an initialization phase in which a voltage of an initialization power source is supplied.

Abstract: A battery module of the present disclosure includes: a cell stack including a plurality of battery cells; a first end plate and a second end plate respectively covering a top surface and a bottom surface of the cell stack; a first upper reinforcing plate and a second upper reinforcing plate located on the first end plate and respectively extending from a side and the other side of the first end plate in a longitudinal direction of the first end plate toward a central portion; a first lower reinforcing plate and a second lower reinforcing plate located on the second end plate and respectively extending from a side and the other side of the second end plate in a longitudinal direction of the second end plate toward a central portion; a first fastening bolt located on a side of the cell stack in a longitudinal direction of the cell stack, and passing through the first upper reinforcing plate, the first end plate, the second end plate, and the first lower reinforcing plate; and a second fastening bolt located on

Abstract: A chip antenna includes a substrate having a concavo-convex pattern on a surface thereof, and a conductor pattern disposed on the surface of the substrate having the concavo-convex pattern, wherein a convex portion extending in one direction and a concave portion extending in one direction are alternately disposed in the concavo-convex pattern.

Abstract: A chip antenna module includes a substrate, a plurality of chip antennas disposed on a first surface of the substrate, and an electronic element mounted on a second surface of the substrate, wherein each of the plurality of chip antennas includes a first ceramic substrate mounted on the first surface of the substrate, a second ceramic substrate opposing the first ceramic substrate, a first patch disposed on the first ceramic substrate, and a second patch disposed on the second ceramic substrate, and the first ceramic substrate and the second ceramic substrate are spaced apart from each other.

Abstract: An array antenna includes an antenna substrate including a first ceramic member, an insertion member and a second ceramic member sequentially stacked, antenna pattern portions arranged on the antenna substrate in an array form, and shielding vias disposed inside the antenna substrate and extending in a thickness direction of the antenna substrate. The shielding vias are disposed in thickness areas of the antenna substrate corresponding to the antenna pattern portions.

Abstract: An antenna includes a first insulating layer; a second insulating layer disposed on the first insulating layer in a height direction; a third insulating layer disposed between the first and second insulating layers, a feed via including a first portion passing through the first insulating layer, a second portion passing through the second insulating layer, and a third portion passing through the third insulating layer and connected to the first and second portions; and an antenna patch disposed on the first insulating layer and fed from the feed via, wherein a permittivity of the third insulating layer is lower than permittivities of the first and second insulating layers, and in a direction perpendicular to the height direction, a width of the third portion is wider than a width of the first portion and/or a width of the second portion.

Abstract: A chip antenna includes a first ceramic substrate, a second ceramic substrate disposed to face the first ceramic substrate, a first patch disposed on the first ceramic substrate to operate as a feed patch, and a second patch disposed on the second ceramic substrate to operate as a radiation patch. One or both of the first ceramic substrate and the second ceramic substrate include a groove, and one or both of the first patch and the second patch is disposed in the groove of the respective first ceramic substrate and second ceramic substrate and protrudes from the groove.