Abstract: A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively.

Abstract: A nonvolatile memory device is programmed by performing a plurality of program loops each comprising sequentially applying first through n-th program pulses (n>1) to a selected wordline connected to a page of memory cells to be programmed, and incrementing each of the first through n-th program pulses prior to a next program loop, wherein the first through n-th program pulses are used to program selected memory cells to respective first through n-th program states, and during application of an i-th program pulse among the first through n-th program pulses (1<i<n), applying a program inhibit voltage to bitlines connected to selected memory cells to be programmed to the first through (i?1)-th program states and applying a program permission voltage to bitlines connected to selected memory cells to be programmed to the i-th through n-th program states.

Abstract: A nonvolatile memory device includes an array of nonvolatile memory cells and a plurality of page buffers configured to receive a plurality of pages of data read from the same page in the array using different read voltage conditions. A control circuit is provided, which is electrically coupled to the plurality of page buffers. The control circuit is configured to perform a test operation by driving the plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits, which are derived from a comparison of at least two of the multiple pages of data read from the same page of nonvolatile memory cells using the different read voltage conditions. An input/output device is provided, which is configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device.

Abstract: A method of programming a nonvolatile memory device including multi-level cells that store multi-bit data, includes performing a pre-programming operation that programs at least some of the multi-level cells to a plurality of intermediate states which are different from an erased state, and performing a main programming operation that programs the multi-level cells to a plurality of target states corresponding to the multi-bit data. At least some of the intermediate program states have threshold voltage distributions that partially overlap each other.

Abstract: A nonvolatile memory device is programmed by performing a plurality of program loops each comprising applying a program voltage to a selected wordline to change a threshold voltage of a selected memory cell, and applying a verification voltage to the selected wordline to verify a program state of the selected memory cell. In each program loop, the nonvolatile memory device determines a program condition and increments the program voltage by an amount determined according to the program condition.

Abstract: A memory device useable with a memory system includes a voltage generator to a plurality of first candidate voltages and a plurality of second candidate voltages, and an X decoder to sequentially apply each of the plurality of first candidate voltages and each of the plurality of second candidate voltages to one or more cells of a memory cell array, and then to apply one of the plurality of first candidate voltages and one of the plurality of second candidate voltages as a first read voltage and a second voltage, respectively, to read data from the cells of the memory cell array according to a characteristic of the cells of the memory cell array.

Abstract: A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage.

Abstract: A non-volatile memory device performs a read operation for compensating for coupling due to an adjacent memory cell. With the read operation of the non-volatile memory device, the coupling effect included in a read result of the selected memory cell is compensated on the basis of a program state of an adjacent memory cell adjacent to the selected memory cell. Toward this end, a read operation for the adjacent memory cell is selectively performed before the selected memory cell is read. Upon sensing of data from the selected memory cell, one or more read operations for the selected memory cell are performed according to the program state of the adjacent memory cell with a read voltage being changed in level depending on the program state of the adjacent memory cell.

Abstract: A method of operating a memory device comprises applying an initial read voltage to a selected wordline to perform a read operation on memory cells connected to the selected wordline, determining whether a read failure occurs with respect to one or more of the memory cells, upon determining that a read failure has occurred with respect to some of the memory cells, determining threshold voltage distribution information for distinct groups of the memory cells, and determining a new read voltage to be applied to the selected wordline based on the threshold voltage distribution information.

Abstract: A memory device includes a memory cell array and a page buffer unit. The memory cell array includes multiple memory cells. The page buffer unit performs a logic operation on data sequentially read from the memory cells at different voltage levels, based on the read data and a read direction of applying the different voltage levels.

Abstract: A memory device comprises a memory cell that is in one of an erase state and first through N-th program states (N>2). The memory device can be read by determining a first read voltage between the erase state and the first program state based on variations of respective threshold voltage distributions of the erase state and the first program state, and determining one among second through N-th read voltages based on variations in respective threshold voltage distributions of two adjacent program states among the first through N-th program states, and determining remaining read voltages among the second through N-th read voltages based on the one read voltage.

Abstract: A method of programming a nonvolatile memory device including multi-level cells that store multi-bit data, includes performing a pre-programming operation that programs at least some of the multi-level cells to a plurality of intermediate states which are different from an erased state, and performing a main programming operation that programs the multi-level cells to a plurality of target states corresponding to the multi-bit data. At least some of the intermediate program states have threshold voltage distributions that partially overlap each other.

Abstract: A nonvolatile memory device includes an array of nonvolatile memory cells and a plurality of page buffers configured to receive a plurality of pages of data read from the same page in the array using different read voltage conditions. A control circuit is provided, which is electrically coupled to the plurality of page buffers. The control circuit is configured to perform a test operation by driving the plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits, which are derived from a comparison of at least two of the multiple pages of data read from the same page of nonvolatile memory cells using the different read voltage conditions. An input/output device is provided, which is configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device.

Abstract: A method is provided for programming a multi-level cell flash memory device. The programming method includes programming a first memory cell of the multi-level call flash memory device to one of first through i-th program states, wherein i is a positive integer, by applying a first program pulse to the first memory cell in a first type programming operation, and programming a second memory cell to one of i+1-th through j-th program states, wherein j is an integer equal to or greater than three, by applying a second program pulse to the second memory cell in a second type programming operation. At least one of a second step voltage, a second bit-line forcing voltage and a second verification operation of the second type programming operation is different from a first step voltage, a first bit-line forcing voltage, and a first verification operation of the first type programming operation, respectively.

Abstract: A nonvolatile memory device is programmed by performing a plurality of program loops each comprising sequentially applying first through n-th program pulses (n>1) to a selected wordline connected to a page of memory cells to be programmed, and incrementing each of the first through n-th program pulses prior to a next program loop, wherein the first through n-th program pulses are used to program selected memory cells to respective first through n-th program states, and during application of an i-th program pulse among the first through n-th program pulses (1<i<n), applying a program inhibit voltage to bitlines connected to selected memory cells to be programmed to the first through (i?1)-th program states and applying a program permission voltage to bitlines connected to selected memory cells to be programmed to the i-th through n-th program states.

Abstract: A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the sensing code to generate a global output signal. The calibrated code is generated by performing a calibration on the sensing code. The local latch unit repeatedly latches the global output signal in response to the address signal to generate a plurality of trim output signals.

Abstract: A nonvolatile memory device is programmed by performing a plurality of program loops each comprising applying a program voltage to a selected wordline to change a threshold voltage of a selected memory cell, and applying a verification voltage to the selected wordline to verify a program state of the selected memory cell. In each program loop, the nonvolatile memory device determines a program condition and increments the program voltage by an amount determined according to the program condition.

Abstract: A memory system comprises a controller that generates a processor clock, and a plurality of memory devices each comprising an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.

Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.