Abstract: A memory management method and apparatus based on an access time in a multi-core system. In the memory management method of the multi-core system, it is easy to estimate the execution time of a task to be performed by a processing core and it is possible to secure the same memory access time when a task is migrated between processing cores by setting a memory allocation order according to distances from the processing cores to the memories in correspondence with the processing cores, translating a logical address to be processed by one of the processing cores according to the set memory allocation order into a physical address of one of the memories, and allocating a memory corresponding to the translated physical address to the processing core.

Abstract: A non-volatile memory device performs a read operation for compensating for coupling due to an adjacent memory cell. With the read operation of the non-volatile memory device, the coupling effect included in a read result of the selected memory cell is compensated on the basis of a program state of an adjacent memory cell adjacent to the selected memory cell. Toward this end, a read operation for the adjacent memory cell is selectively performed before the selected memory cell is read. Upon sensing of data from the selected memory cell, one or more read operations for the selected memory cell are performed according to the program state of the adjacent memory cell with a read voltage being changed in level depending on the program state of the adjacent memory cell.

Abstract: A nonvolatile memory device includes a memory cell array, a data scanning unit, and a program unit. The memory cell array includes a plurality of memory cells, where each of the memory cells is programmable to store data have a first logic value or a second logic value. The data scanning unit is configured to search among a plurality of data to be programmed in the memory cells to identify data having the second logic value. The program unit is configured to group the identified data having the second logic value, and to program at least a portion of the group of identified data at a same time into the memory cells.

Abstract: A method of reading data in a non-volatile memory device based on the logic level of a selection bit of an address, determines an order of reading a first and second bits of data stored in one multi-level memory cell corresponding to the address based on the logic level of the selection bit, and senses and outputs the first and second bits of data according to the determined order of reading. The method of reading data in a non-volatile memory device and the method of inputting and outputting data in a non-volatile memory device may reduce the initial read time by selecting the order of reading the first and second bits of data stored in the multi-level memory cell and reading the data according the order based on the start address.

Abstract: A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

Abstract: A method of erasing data in a flash memory device, including erasing data in at least one flash memory cell using a first erase voltage; detecting whether the at least one flash memory cell has a threshold voltage less than a first voltage; programming the at least one flash memory cell by varying the threshold voltage of the at least one flash memory cell using a second voltage that is greater than the first voltage if the detecting step detects the threshold voltage is less than the first voltage; maintaining the threshold voltage of the at least one flash memory cell if the detecting step detects the threshold voltage is greater than the first voltage; and verifying the at least one flash memory cell using a first verification voltage.

Abstract: A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the sensing code to generate a global output signal. The calibrated code is generated by performing a calibration on the sensing code. The local latch unit repeatedly latches the global output signal in response to the address signal to generate a plurality of trim output signals.

Abstract: A nonvolatile memory device performs a program operation on selected memory cells by determining a level of a program voltage based on a degree of deterioration of the memory cells, and executing the program operation using the program voltage.

Abstract: A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array. The device further includes a read/write controller configured to cause the read/write circuit to perform a reading/writing operation in response to the read/write flag signal provided from the command decoder, and a reprogram controller configured to cause the read/write controller to perform a reprogramming operation in response to the reprogram flag signal. Methods of reprogramming a memory device include determining whether the memory device is in a busy state, delaying a reprogramming operation if the memory device is in a busy state, and executing the reprogramming operation when the memory device has turned to a standby state from the busy state.

Abstract: Disclosed is a nonvolatile memory device and programming method of a nonvolatile memory device. The programming method of the nonvolatile memory device includes conducting a first programming operation for a memory cell, retrieving original data from the memory cell after the first programming operation, and conducting a second programming operation with reference to the original data and a second verifying voltage higher than a first verifying voltage of the first programming operation.

Abstract: A method of reading data in a non-volatile memory device based on the logic level of a selection bit of an address, determines an order of reading a first and second bits of data stored in one multi-level memory cell corresponding to the address based on the logic level of the selection bit, and senses and outputs the first and second bits of data according to the determined order of reading. The method of reading data in a non-volatile memory device and the method of inputting and outputting data in a non-volatile memory device may reduce the initial read time by selecting the order of reading the first and second bits of data stored in the multi-level memory cell and reading the data according the order based on the start address.

Abstract: A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.

Abstract: A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.

Abstract: A method of erasing data in a flash memory device, including erasing data in at least one flash memory cell using a first erase voltage; detecting whether the at least one flash memory cell has a threshold voltage less than a first voltage; programming the at least one flash memory cell by varying the threshold voltage of the at least one flash memory cell using a second voltage that is greater than the first voltage if the detecting step detects the threshold voltage is less than the first voltage; maintaining the threshold voltage of the at least one flash memory cell if the detecting step detects the threshold voltage is greater than the first voltage; and verifying the at least one flash memory cell using a first verification voltage.

Abstract: A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

Abstract: In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.

Abstract: A test system includes a memory device having a data I/O circuit connected to a data write-in path and a data read-out path. During test mode, the data I/O circuit retains a copy of test pattern data received in the I/O circuit via the data write-in path as output test data before the test pattern data is stored in a memory cell array as write data. The test system also includes a test device generating the test pattern data, receiving the output test data from the memory device, comparing the output test data with the test pattern data, and generating an error detection signal on the basis of the comparison. The error detection signal indicates the presence or absence of a defect in the data write-in or read-out path.

Abstract: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.

Abstract: A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

Abstract: A method for computing maximum traffic capacitance of a base station using a virtual call in the digital mobile communication system in such a way that an operator at operating terminal for Base Station Manager (BSM) inputs call-set-request instructions using the virtual call to maintain and repair the digital mobile communication system so that traffic state is set between mobile stations in the service area of test base station and a vocoder of a Base Station Controller (BSC) to compute maximum traffic capacitance of the test base station. An operator at operation terminal inputs call set information by operator instruction as much as mobile station numbers to be tested to compute maximum traffic capacitance of the base station. The BSM inputs a virtual call-set-request-instruction by means of a virtual call-set-start-flag.