Patents by Inventor Jae-Youn Youn
Jae-Youn Youn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11114139Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.Type: GrantFiled: February 10, 2021Date of Patent: September 7, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
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Publication number: 20210166740Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.Type: ApplicationFiled: February 10, 2021Publication date: June 3, 2021Inventors: Hyun-Sung SHIN, Ik-Joon CHOI, So-Young KIM, Tae-Kyu BYUN, Jae-Youn YOUN
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Patent number: 10923165Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.Type: GrantFiled: January 15, 2020Date of Patent: February 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
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Patent number: 10684793Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.Type: GrantFiled: March 17, 2017Date of Patent: June 16, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hoi-ju Chung, Su-a Kim, Mu-jin Seo, Hak-soo Yu, Jae-youn Youn, Hyo-jin Choi
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Publication number: 20200152244Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
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Patent number: 10553260Abstract: A stacked memory device includes; a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.Type: GrantFiled: July 18, 2018Date of Patent: February 4, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
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Publication number: 20190096453Abstract: A stacked memory device includes; a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.Type: ApplicationFiled: July 18, 2018Publication date: March 28, 2019Inventors: HYUN-SUNG SHIN, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
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Patent number: 9875155Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.Type: GrantFiled: December 7, 2016Date of Patent: January 23, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-soo Sohn, Kwang-il Park, Chul-woo Park, Jong-pil Son, Jae-youn Youn, Hoi-ju Chung
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Publication number: 20170192721Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.Type: ApplicationFiled: March 17, 2017Publication date: July 6, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Hoi-ju CHUNG, Su-a KIM, Mu-jin SEO, Hak-soo YU, Jae-youn YOUN, Hyo-jin CHOI
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Patent number: 9685218Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.Type: GrantFiled: August 15, 2016Date of Patent: June 20, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Soo Sohn, Chul-Woo Park, Si-Hong Kim, Kwang-Il Park, Jae-Youn Youn
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Patent number: 9632856Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.Type: GrantFiled: January 11, 2016Date of Patent: April 25, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoi-ju Chung, Su-a Kim, Mu-jin Seo, Hak-soo Yu, Jae-youn Youn, Hyo-jin Choi
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Patent number: 9626244Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.Type: GrantFiled: March 13, 2014Date of Patent: April 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-soo Sohn, Kwang-il Park, Chul-woo Park, Jong-pil Son, Jae-youn Youn, Hoi-ju Chung
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Publication number: 20170091027Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.Type: ApplicationFiled: December 7, 2016Publication date: March 30, 2017Inventors: Young-soo Sohn, Kwang-il Park, Chul-woo Park, Jong-pil Son, Jae-youn Youn, Hoi-ju Chung
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Patent number: 9552867Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.Type: GrantFiled: January 2, 2015Date of Patent: January 24, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Soo Sohn, Uk-Song Kang, Kwang-Il Park, Chul-Woo Park, Hak-Soo Yu, Jae-Youn Youn
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Patent number: 9536586Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.Type: GrantFiled: October 15, 2014Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Soo Sohn, Chul-Woo Park, Si-Hong Kim, Kwang-Il Park, Jae-Youn Youn
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Publication number: 20160351244Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.Type: ApplicationFiled: August 15, 2016Publication date: December 1, 2016Inventors: Young-Soo SOHN, Chul-Woo PARK, Si-Hong KIM, KWANG-IL PARK, Jae-Youn YOUN
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Patent number: 9460816Abstract: The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region.Type: GrantFiled: July 28, 2014Date of Patent: October 4, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Youn Youn, Chul-Woo Park, Hak-Soo Yu
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Patent number: 9390778Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.Type: GrantFiled: July 13, 2015Date of Patent: July 12, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su-A Kim, Dae-Sun Kim, Dae-Jeong Kim, Sung-Min Ryu, Kwang-Il Park, Chul-Woo Park, Young-Soo Sohn, Jae-Youn Youn
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Publication number: 20160124784Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.Type: ApplicationFiled: January 11, 2016Publication date: May 5, 2016Inventors: Hoi-ju CHUNG, Su-a KIM, Mu-jin SEO, Hak-soo YU, Jae-youn YOUN, Hyo-jin CHOI
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Patent number: 9330743Abstract: A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.Type: GrantFiled: April 3, 2015Date of Patent: May 3, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-Kyung Kim, Kee-Won Kwon, Su-A Kim, Chul-Woo Park, Jae-Youn Youn