Abstract: Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.

Abstract: A semiconductor memory device includes at least one sense amplifier, a controller and a sense amplifier driver. The sense amplifier includes a PMOS sense amplifier and an NMOS sense amplifier configured to be respectively activated in response to a first supply voltage and a second supply voltage, and to sense and amplify a voltage difference between a corresponding bit line pair. The controller is configured to set an operating mode in response to an external command, to control activation timing of a PMOS drive activation signal and an NMOS drive activation signal according to the set operating mode, and to output the PMOS drive activation signal and the NMOS drive activation signal. The sense amplifier driver is configured to apply the first and second supply voltages to the PMOS and NMOS sense amplifiers, respectively, in response to the PMOS drive activation signal and the NMOS drive activation signal.

Abstract: The boosting voltage generating circuit of example embodiments may include a boosting level detection unit, a first boosting pump, and a second boosting pump. The boosting level detection unit may be configured to generate a target level detection signal and a margin level detection signal. The target level detection signal may have a logic state according to a level of a boosting voltage compared with a target voltage level, and the margin level detection signal may have a logic state according to a level of the boosting voltage compared with a margin voltage level, the margin voltage level being higher than the target voltage level. The first boosting pump may be controlled based on a target voltage level. The second boosting pump may be controlled based on a margin voltage level. According to the boosting voltage generating circuit of example embodiments, overshoot of the boosting voltage by the second boosting pump may remarkably decrease.

Abstract: A semiconductor memory device includes a fuse box including a plurality of address antifuse circuits, each address antifuse circuit outputting an address fuse signal according to a program state of an antifuse included in the corresponding address antifuse circuit, an address comparator including a plurality of address comparison signal generators, each address comparison signal generator combining a first test signal for determining an initial defect of the antifuse and a corresponding bit of an externally applied address signal to generate a test address, and comparing the test address with the address fuse signal to generate an address comparison signal, and a redundant enable signal generator for enabling a redundancy enable signal in response to a plurality of address comparison signals.

Abstract: An internal voltage generator includes a control section and a switchable internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a partial array self refresh (PASR) signal. The internal voltage may be supplied to banks selected by the bank PASR signal, thereby enabling refresh operations in the entire bank, or an internal voltage adequate to partially enable refresh operations in all the banks may be supplied. Thus, unnecessary power consumption may be effectively controlled.

Abstract: Semiconductor memory devices having hierarchical word line structures are provided in which sub-word line driver circuitry is designed with layout patterns that enable increased integration density and high performance operation.

Abstract: Multi-bank semiconductor memory devices are provided having optimized memory block layouts and data line routing to enable chip size reduction and increase operating memory access speed.

Abstract: The boosting voltage generating circuit of example embodiments may include a boosting level detection unit, a first boosting pump, and a second boosting pump. The boosting level detection unit may be configured to generate a target level detection signal and a margin level detection signal. The target level detection signal may have a logic state according to a level of a boosting voltage compared with a target voltage level, and the margin level detection signal may have a logic state according to a level of the boosting voltage compared with a margin voltage level, the margin voltage level being higher than the target voltage level. The first boosting pump may be controlled based on a target voltage level. The second boosting pump may be controlled based on a margin voltage level. According to the boosting voltage generating circuit of example embodiments, overshoot of the boosting voltage by the second boosting pump may remarkably decrease.

Abstract: An internal voltage generator includes a control section and a switchable internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a partial array self refresh (PASR) signal. The internal voltage may be supplied to banks selected by the bank PASR signal, thereby enabling refresh operations in the entire bank, or an internal voltage adequate to partially enable refresh operations in all the banks may be supplied. Thus, unnecessary power consumption may be effectively controlled.

Abstract: An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address.

Abstract: An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address.

Abstract: An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address.

Abstract: An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address.

Abstract: An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address.

Abstract: An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address.

Abstract: Integrated buffer circuits which are less susceptible to noise and provide TTL-to-CMOS signal conversion capability include a first TTL-compatible inversion buffer, a second CMOS-compatible inversion buffer having an input electrically coupled to an output of the first inversion buffer and a preferred pull-up (or pull-down) circuit to improve noise immunity. The preferred circuit pulls the output of the first inversion buffer to a potential of the first reference signal line (e.g., Vdd) in response to a signal at an output of the second inversion buffer and a signal at an input of the first inversion buffer. This circuit comprises a first field effect transistor having a gate electrode electrically coupled to the output of the second inversion buffer and a second field effect transistor having a gate electrode electrically coupled to the input of the first inversion buffer.

Abstract: A semiconductor memory device with a cascaded burn-in test capability for a plurality of memory cell blocks. A delayed feedback signal is communicated between memory cell block selection circuits to create the cascade burn-in.