Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.

Abstract: An indoor unit of an air conditioner having improved structures of suction, discharge and/or flow passages which may increase operation efficiency, reduce noises and realize a compact size. The indoor unit includes a housing comprising a front panel and a rear panel coupled to a rear portion of the front panel, at least one discharge outlet exposed to a front of the front panel, at least one suction inlet formed in the rear panel at a position corresponding to the discharge outlet, at least one heat exchanger disposed at a front portion of the suction inlet to absorb heat from air introduced through the suction inlet or transfer heat to the air introduced through the suction inlet, and at least one diagonal flow fan disposed between the heat exchanger and the discharge outlet to suction air passing through the heat exchanger and discharge the air through the discharge outlet.

Abstract: An audio signal processing method and an audio signal processing apparatus for synchronizing audio based on synchronization error between audio signals.

Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Abstract: Disclosed are an apparatus and method for storing and displaying images in a picture archiving and communication system (PACS). The apparatus, comprising: a processor configured to: generate a two-dimensional (2D) medical image for a three-dimensional (3D) medical image at each of reference points of a predetermined (3D) screen model; and store the generated (2D) medical image along with attribute information related to the generation of the (2D) medical image to a storage device or a memory.

Abstract: The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region.

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Abstract: Provided is a method of operating an acoustic event detecting apparatus including: receiving an acoustic input; extracting frequency characteristics of the acoustic input; determining whether a first acoustic event has occurred by analyzing the extracted frequency characteristics; and in response to determining that the first acoustic event has occurred, acquiring data about at least one of a sound, an image, and a video from an environment outside of the acoustic event detecting apparatus and transmitting the data to a first device.

Abstract: A surface acoustic wave device includes: a piezoelectric substrate; an interdigital transducer disposed on the piezoelectric substrate, the interdigital transducer being configured to transduce a driving signal into a surface acoustic wave, and transduce a reflected surface acoustic wave into a response signal; a reflector arranged on the piezoelectric substrate and configured to reflect the surface acoustic wave input from the interdigital transducer; a first antenna disposed on the piezoelectric substrate, the first antenna extending radially from the interdigital transducer, and the first antenna being configured to receive the driving signal and transmit the response signal; and a second antenna disposed on the piezoelectric substrate, the second antenna extending radially from the interdigital transducer to be asymmetrical with respect to the first antenna, and the second antenna being configured to receive the driving signal and transmit the response signal.

Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.