Patents by Inventor Jae Youn

Jae Youn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory cores of resistive type memory devices, resistive type memory devices and method of sensing data in the same
    Patent number: 9330743
    Abstract: A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: May 3, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-Kyung Kim, Kee-Won Kwon, Su-A Kim, Chul-Woo Park, Jae-Youn Youn
  • SPEECH ENHANCEMENT METHOD AND APPARATUS FOR SAME
    Publication number: 20160111113
    Abstract: A speech enhancement method is provided. The speech enhancement method includes: estimating a direction of a speaker by using an input signal, generating direction information indicating the estimated direction, detecting speech of a speaker based on a result of the estimating the direction, and enhancing the speech of the speaker by using the direction information based on a result of the detecting the speech.
    Type: Application
    Filed: May 30, 2014
    Publication date: April 21, 2016
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-youn CHO, Weiwei CUI, Seung-yeol LEE
  • Memory system for continuously mapping addresses of a memory module having defective locations
    Patent number: 9318168
    Abstract: In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., LTD.
    Inventors: Chul-Woo Park, Dong-Soo Kang, Su-A Kim, Jun-hee Yoo, Hak-Soo Yu, Jae-Youn Youn, Sung-hyun Lee, Kyoung-Heon Jeong, Hyo-Jin Choi, Young-Soo Sohn
  • Texture-etchant composition for crystalline silicon wafer and method for texture-etching (1)
    Patent number: 9305792
    Abstract: Disclosed herein is an etching composition for texturing a crystalline silicon wafer, comprising, based on a total amount of the composition: (A) 0.1 to 20 wt % of an alkaline compound; (B) 0.1 to 50 wt % of a cyclic compound having a boiling point of 100° C. or more; (C) 0.00001 to 10 wt % of a silica-containing compound; and (D) residual water. The etching composition can maximize the absorbance of light of the surface of a crystalline silicon wafer.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: April 5, 2016
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Hyung-Pyo Hong, Jae-Youn Lee, Dae-Sung Lim
  • ROGOWSKI COIL AND CURRENT MEASUREMENT SENSOR INCLUDING THE SAME
    Publication number: 20160077133
    Abstract: There is provided a current measurement sensor including: a rogowski coil having a winding coil disposed on an outer circumference part of a coaxial coil; a body case to which one end and the other end of the rogowski coil are coupled, so that the rogowski coil forms a loop; and a coupling member coupling the rogowski coil to the body case, wherein the coupling member includes: a coil coupling member having one side coupled to the rogowski coil and the other side coupled to the body case, and a case coupling member coupled to the body case and covering a coupling part between the coil coupling member and the body case.
    Type: Application
    Filed: September 9, 2015
    Publication date: March 17, 2016
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Chan LEE, Kwang Myung KIM, Se Jin SEO, Jae Youn JEONG
  • Interface circuit, and semiconductor device and liquid crystal display device including the same
    Patent number: 9281818
    Abstract: A method of reducing power consumption caused by leakage current in an interface circuit between modules that are driven by different power sources is disclosed. The interface circuit includes an output driver that operates by a first power supply voltage in a first mode and does not operate in a second mode in which the first power supply voltage is prevented from being applied, an input buffer that is operated by a second power supply voltage in the first and second modes, and a transmission line that connects an output terminal of the output driver to an input terminal of the input buffer. The interface circuit further includes a current leakage prevention circuit that prevents, in the second mode, a current leakage in the input buffer between a second power supply voltage source that supplies the second power supply voltage and a ground voltage source.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: March 8, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hoon Lim, Ji-Hyun Lee, Jae-youn Lee
  • SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    Publication number: 20160064056
    Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.
    Type: Application
    Filed: July 13, 2015
    Publication date: March 3, 2016
    Inventors: SU-A KIM, Dae-Sun KIM, Dae-Jeong KIM, Sung-Min RYU, Kwang-II PARK, Chul-Woo PARK, Young-Soo SOHN, Jae-Youn YOUN
  • Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices
    Patent number: 9268636
    Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: February 23, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-ju Chung, Su-A Kim, Mu-Jin Seo, Hak-Soo Yu, Jae-Youn Youn, Hyo-Jin Choi
  • Conductive atomic force microscope and method of operating the same
    Patent number: 9261532
    Abstract: A conductive atomic force microscope including a plurality of probe structures each including a probe and a cantilever connected thereto, a power supplier applying a bias voltage, a current detector detecting a first current flowing between a sample object and each of the probes and a second current flowing between a measurement object and each of the probes, and calculating representative currents for the sample and measurement objects based on the first and second currents, respectively, and a controller calculating a ratio between representative currents of the sample object measured by each of the probe structures, calculating a scaling factor for scaling the representative current with respect to the measurement object measured by each of the probes, and determine a reproducible current measurement value based on the second measurement current and the scaling factor may be provided.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: February 16, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-woo Kim, Woo-seok Ko, Young-hwan Kim, Jeong-hoi Kim, Baek-man Sung, Hyung-su Son, Chae-ho Shin, Yu-sin Yang, Jae-youn Wi, Sang-kil Lee, Chung-sam Jun
  • CONDUCTIVE ATOMIC FORCE MICROSCOPE AND METHOD OF OPERATING THE SAME
    Publication number: 20160033550
    Abstract: A conductive atomic force microscope including a plurality of probe structures each including a probe and a cantilever connected thereto, a power supplier applying a bias voltage, a current detector detecting a first current flowing between a sample object and each of the probes and a second current flowing between a measurement object and each of the probes, and calculating representative currents for the sample and measurement objects based on the first and second currents, respectively, and a controller calculating a ratio between representative currents of the sample object measured by each of the probe structures, calculating a scaling factor for scaling the representative current with respect to the measurement object measured by each of the probes, and determine a reproducible current measurement value based on the second measurement current and the scaling factor may be provided.
    Type: Application
    Filed: April 23, 2015
    Publication date: February 4, 2016
    Inventors: Hyun-woo KIM, Woo-seok KO, Young-hwan KIM, Jeong-hoi KIM, Baek-man SUNG, Hyung-su SON, Chae-ho SHIN, Yu-sin YANG, Jae-youn WI, Sang-kil LEE, Chung-sam JUN
  • MEMORY CORES OF RESISTIVE TYPE MEMORY DEVICES, RESISTIVE TYPE MEMORY DEVICES AND METHOD OF SENSING DATA IN THE SAME
    Publication number: 20150364178
    Abstract: A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.
    Type: Application
    Filed: April 3, 2015
    Publication date: December 17, 2015
    Inventors: Chan-Kyung KIM, Kee-Won KWON, Su-A KIM, Chul-Woo PARK, Jae-Youn YOUN
  • SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    Publication number: 20150309743
    Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.
    Type: Application
    Filed: January 2, 2015
    Publication date: October 29, 2015
    Inventors: Young-Soo SOHN, Uk-Song KANG, KWANG-IL PARK, Chul-Woo PARK, Hak-Soo YU, Jae-Youn YOUN
  • SEMICONDUCTOR DEVICE
    Publication number: 20150311334
    Abstract: A semiconductor device may include a drift layer having a first conductivity-type; a body region having a second conductivity-type and disposed on the drift layer; first semiconductor regions having the second conductivity-type and disposed to be spaced apart from each other below the drift layer; and second semiconductor regions having the first conductivity-type and disposed between the first semiconductor regions below the drift layer.
    Type: Application
    Filed: July 15, 2014
    Publication date: October 29, 2015
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Chang Su JANG, Ji Hye KIM, Kyu Hyun MO, Dong Soo SEO, Sun Jae YOUN
  • APPARATUS FOR MEASURING INNER DIAMETER
    Publication number: 20150300811
    Abstract: There is provided an apparatus for measuring an inner diameter, the apparatus including: an optical unit irradiating light to an object to be measured, and receiving the light therefrom; a measurement auxiliary member inserted into the object to improve measurement precision; and a calculating unit calculating an inner diameter of the object by interference between light reflected and received from an inner peripheral surface of the object and light reflected and received from an outer peripheral surface of the measurement auxiliary member.
    Type: Application
    Filed: July 18, 2014
    Publication date: October 22, 2015
    Inventors: Nak Hyun SEONG, Min Jung KIM, Jae Youn JEONG
  • Semiconductor memory device performing a refresh operation, and memory system including the same
    Patent number: 9147461
    Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The refresh circuit is configured to: perform a second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation, and not perform the second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation. Whether the refresh control circuit performs or does not perform the second burst refresh operation is based on a comparison between an entering time for the self refresh operation of the memory cell rows and a reference time.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: September 29, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Youn Youn, So-Young Kim, Kwang-Sook Noh, Sang-Jae Rhee, Hyun-Chul Yoon, Yoon-Jae Lee, Jung-Bae Lee, Joo-Sun Choi
  • MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME
    Publication number: 20150243338
    Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.
    Type: Application
    Filed: October 15, 2014
    Publication date: August 27, 2015
    Inventors: Young-Soo SOHN, Chul-Woo PARK, Si-Hong KIM, KWANG-IL PARK, Jae-Youn YOUN
  • Display screen portion with icon
    Patent number: D748672
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: February 2, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Youn Jeong, Bo-Ran Lee, Jung-Ah Seung, Gu-Hyun Yang, Jong-Hoon Lee
  • Display screen or portion thereof with animated graphical user interface
    Patent number: D749625
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: February 16, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gu-Hyun Yang, Bo-Ran Lee, Sang-Hee Bae, Jong-Hoon Lee, Jae-Youn Jeong
  • Display screen or portion thereof with icon
    Patent number: D754737
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: April 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Youn Jeong, Jong-Hoon Lee, Gu-Hyun Yang
  • Display screen portion with icon
    Patent number: D754748
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Youn Jeong, Bo-Ran Lee, Jung-Ah Seung, Gu-Hyun Yang, Jong-Hoon Lee