Patents by Inventor Jae Youn

Jae Youn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device performing a refresh operation, and memory system including the same
    Patent number: 9147461
    Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The refresh circuit is configured to: perform a second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation, and not perform the second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation. Whether the refresh control circuit performs or does not perform the second burst refresh operation is based on a comparison between an entering time for the self refresh operation of the memory cell rows and a reference time.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: September 29, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Youn Youn, So-Young Kim, Kwang-Sook Noh, Sang-Jae Rhee, Hyun-Chul Yoon, Yoon-Jae Lee, Jung-Bae Lee, Joo-Sun Choi
  • MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME
    Publication number: 20150243338
    Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.
    Type: Application
    Filed: October 15, 2014
    Publication date: August 27, 2015
    Inventors: Young-Soo SOHN, Chul-Woo PARK, Si-Hong KIM, KWANG-IL PARK, Jae-Youn YOUN
  • Volatile memory device capable of relieving disturbances of adjacent memory cells and refresh method thereof
    Patent number: 9087602
    Abstract: Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reach a reference value; and performing a refresh operation on the second memory area in response to the alert signal.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: July 21, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Youn Youn, Su-A Kim, Chul-Woo Park, Young-Soo Sohn
  • Semiconductor memory device and refresh method thereof
    Patent number: 9076504
    Abstract: A semiconductor memory device and a self-refresh method of the semiconductor memory device. The semiconductor memory device includes: a memory cell array including one or more memory cells; a sense amplifier connected to a sensing line and a complementary sensing line and sensing/amplifying data stored in the one or more memory cells; and a sense amplifier control circuit sequentially supplying a first voltage and a second voltage having different levels to the sense amplifier through the sensing line during a refresh operation.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: July 7, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Ho Lee, Kyu-Chang Kang, Hyo-Chang Kim, Jae-Youn Youn, Sang-Jae Rhee
  • Semiconductor memory device and memory system including the same
    Patent number: 9064603
    Abstract: A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes first and second sub arrays, the first sub array includes a first set of bank arrays, and the second sub array includes a second set of bank arrays. Each of the upper and lower bank arrays includes first and second portions having different timing parameters with respect to each other. The control logic controls access to the first and second portions such that read/write operation is performed on the first and second portions.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: June 23, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Youn Youn, Su-A Kim, Hyo-Jin Choi, Chul-Woo Park, Hak-Soo Yu
  • APPARATUS FOR PREPARING ENZYME-IMMOBILIZED BEADS AND METHOD FOR PREPARING ENZYME-IMMOBILIZED BEADS USING SAME
    Publication number: 20150125922
    Abstract: The present invention relates to an apparatus for preparing enzyme-immobilized beads used for preparation of tagatose, and a method for preparing enzyme-immobilized beads using the same. More specifically, the present invention relates to an apparatus for preparing enzyme-immobilized beads, comprising a nozzle with an inside diameter of 0.1-1 mm having a cylindrical lower end and comprising a cut-type liquid outlet (cut perpendicularly to the vertical axis of the nozzle) formed at the lower end, and a method for preparing enzyme-immobilized beads using the same.
    Type: Application
    Filed: May 10, 2013
    Publication date: May 7, 2015
    Inventors: Soon Chul Kim, Seong Bo Kim, Jae Youn Lim, Kwang Jin An, Jin Ha Kim
  • SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    Publication number: 20150089327
    Abstract: The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region.
    Type: Application
    Filed: July 28, 2014
    Publication date: March 26, 2015
    Inventors: Jae-Youn YOUN, Chul-Woo PARK, Hak-Soo YU
  • Use of lignan-type compounds or extract of nutmeg or aril of nutmeg comprising the same
    Patent number: 8969408
    Abstract: The present invention relates to a new use of lignan-type compounds or an extract of nutmeg or aril of nutmeg comprising the same. More particularly, the present invention relates to a composition for skin whitening comprising a lignan-type compound or an extract of nutmeg or aril of nutmeg comprising the same. Because the lignan compound represented by Chemical Formulas 1 to 3 or the extract of nutmeg or aril of nutmeg has superior skin whitening activity by inhibiting melanin production and tyrosinase activity, it can be used for the preparation of a cosmetic composition, food composition or pharmaceutical composition for skin whitening.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: March 3, 2015
    Assignees: Biocare Co., Ltd., Newtree Co., Ltd.
    Inventors: Jae Kwan Hwang, Yu-Mi Cho, Gyu Hoi Kim, Jeong Hwan Kim, Hae Ji Lee, Do Un Kim, Hee Chul Chung, Jae Youn Chung, Hyun In Oh
  • MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, OPERATING METHOD THEREOF
    Publication number: 20150049570
    Abstract: In one embodiment, the memory device includes at least one memory bank including first and second subbanks, and control logic configured to control storing data into the memory bank. The control logic is configured to activate the first subbank and to precharge the second subbank in response to a first activate command for the first subbank.
    Type: Application
    Filed: August 4, 2014
    Publication date: February 19, 2015
    Inventors: Sung-Hyun LEE, Jun-Hee YOO, Dong-Soo KANG, Sua KIM, Hak-Soo YU, Jae-Youn YOUN, Hyo-Jin CHOI
  • VOLATILE MEMORY DEVICE AND REFRESH METHOD THEREOF
    Publication number: 20140355332
    Abstract: Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reach a reference value; and performing a refresh operation on the second memory area in response to the alert signal.
    Type: Application
    Filed: March 19, 2014
    Publication date: December 4, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-Youn YOUN, Su-A KIM, Chul-Woo PARK, Young-Soo SOHN
  • MEMORY DEVICE FOR PERFORMING ERROR CORRECTION CODE OPERATION AND REDUNDANCY REPAIR OPERATION
    Publication number: 20140317469
    Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.
    Type: Application
    Filed: March 13, 2014
    Publication date: October 23, 2014
    Inventors: Young-soo Sohn, Kwang-il Park, Chul-woo Park, Jong-pil Son, Jae-youn Youn, Hoi-ju Chung
  • MEMORY SYSTEM
    Publication number: 20140310481
    Abstract: A memory system includes a memory controller to control a first memory device and a second memory device. The first and second memory devices are different in terms of at least one of physical distance from the memory controller, a manner of connection to the memory controller, error correction capability, or memory supply voltage. The first and second memory devices also have different latencies.
    Type: Application
    Filed: April 9, 2014
    Publication date: October 16, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi Ju CHUNG, Su A KIM, Chul Woo PARK, Hak Soo YU, Jae Youn YOUN, Jung Bae LEE, Hyo Jin CHOI
  • Use of lignan compounds for treating or preventing inflammatory disease
    Patent number: 8853264
    Abstract: The present invention relates to the use of lignan compounds for treating or preventing an inflammatory disease. More particularly, it relates to a method for preventing or treating an inflammatory disease, comprising administering to a subject in need thereof an effective amount of macelignan represented by Chemical Formula I or a pharmaceutically acceptable salt thereof. The lignan compound has the effect of inhibiting inflammatory reactions by inhibiting the production or expression of inflammation mediators NO, iNOS, PGE2, COX-2 and TNF-? and by treating or preventing inflammatory disease in vivo. Accordingly, the lignan compound or a Myristica fragrans extract will be highly useful for the treatment or prevention of an inflammatory disease.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: October 7, 2014
    Assignees: Newtree Industry Co., Ltd.
    Inventors: Jae-Kwan Hwang, Do-Un Kim, Jae-Youn Chung, Hee-Chul Chung, Kyu-Lee Han
  • SEMICONDUCTOR MEMORY DEVICE HAVING ASYMMETRIC ACCESS TIME
    Publication number: 20140268978
    Abstract: A semiconductor memory device may include a plurality of data input/output DQ pads and a plurality of first and second memory cell arrays. Each path of a first set of data paths from each of the plurality of first memory cell arrays to a corresponding DQ pad is physically shorter than each path of a second set of data paths from each of the plurality of second memory cell arrays to the corresponding DQ pad. Each of the plurality of first memory cell arrays is a designated first-speed access cell array and each of the plurality of second memory cell arrays is a designated second-speed access cell array, the second-speed being slower than the first-speed. A size of the each of the plurality of first memory cell arrays is smaller than a size of the each of the plurality of second memory cell arrays.
    Type: Application
    Filed: December 30, 2013
    Publication date: September 18, 2014
    Applicants: SAMSUNG ELECTRONICS CO., LTD., SNU R&DB FOUNDATION
    Inventors: Hyo-Jin CHOI, Su-A KIM, Young-Hoon SON, Jung-Ho AHN, Hak-Soo YU, Jae-Youn YOUN
  • SEMICONDUCTOR MEMORY DEVICES INCLUDING ERROR CORRECTION CIRCUITS AND METHODS OF OPERATING THE SEMICONDUCTOR MEMORY DEVICES
    Publication number: 20140245105
    Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.
    Type: Application
    Filed: June 5, 2013
    Publication date: August 28, 2014
    Inventors: Hoi-ju CHUNG, Su-A KIM, Mu-Jin SEO, Hak-Soo YU, Jae-Youn YOUN, Hyo-Jin CHOI
  • Method and apparatus for detecting voice activity by using signal and noise power prediction values
    Patent number: 8744842
    Abstract: A robust method and apparatus to detect voice activity based on the power level of an audio frame. The method may include performing primary active/non-active voice period determination of an input audio frame according to a power level of the audio frame, extracting a noise power prediction value and a signal power prediction value by referring to power levels of current and previous audio frames according to a primary active/non-active voice period determination value, and performing secondary active/non-active voice period determination for the input audio frame by comparing the extracted signal power prediction value with the extracted noise power prediction value.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: June 3, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-youn Cho
  • MEMORY SYSTEM AND METHOD OF MAPPING ADDRESS USING THE SAME
    Publication number: 20140149652
    Abstract: In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 29, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Woo PARK, Dong-Soo KANG, Su-A KIM, Jun-hee YOO, Hak-Soo YU, Jae-Youn YOUN, Sung-hyun LEE, Kyoung-Heon JEONG, Hyo-Jin CHOI, Young-Soo SOHN
  • INDOOR UNIT OF AIR CONDITIONER AND METHOD OF CONTROLLING THE SAME
    Publication number: 20140096941
    Abstract: An indoor unit of an air conditioner has an improved discharge structure of air. The indoor unit of an air conditioner includes a panel which defines an external appearance thereof and has an opening, a mixed flow fan which is located within the panel, a heat exchanger unit which is located rearward of the mixed flow fan, an inlet port which is located rearward of the heat exchanger unit so that air is suctioned from rearward of the heat exchanger unit to be introduced into the mixed flow fan, an outlet port which is exposed forward of the panel through the opening so that the air passing though the mixed flow fan is discharged through a front portion of the panel, and a plurality of circular louvers to open and close the outlet port by moving outwards from a center of the outlet port.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 10, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeon Seob YUN, Jung Ho KIM, Jin Baek KIM, Hae Gyun SHIN, Jin Gyun KIM, Woo Seog SONG, Moon Sun SHIN, Jae Youn CHO, Chang Woo JUNG, Hyoung Seo CHOI, Dong Gi HAN, Jun HWANG
  • SYSTEM AND METHOD FOR DETERMINING TUMOR INVASIVENESS
    Publication number: 20140087411
    Abstract: A method of determining invasion potential of a tumor cell includes exposing a tumor cell to an activity sensor; after exposing the tumor cell to the activity sensor, stimulating the tumor cell to cause a response in the cell that is reported by the activity sensor; detecting the level of response after stimulation of the tumor cell; and determining the invasion potential of the tumor cell based on the response. A system for determining the invasion potential of a tumor cell includes a sample stage that supports the tumor cell; a stimulator that focuses energy on the tumor cell to stimulate the tumor cell; and an imaging apparatus that observes an effect of the beam on the tumor cell.
    Type: Application
    Filed: September 27, 2013
    Publication date: March 27, 2014
    Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Andrew C. Weitz, Nan Sook Lee, Jae Youn Hwang, Robert H. Chow, K. Kirk Shung
  • Charge pump, a method for controlling the same, and a display driving system comprising the charge pump
    Patent number: 8674750
    Abstract: Disclosed is a charge pump and a method of controlling the charge pump. The charge pump including a charge pumping unit to boost a first voltage in response to a clock signal, the first voltage being boosted to a second voltage having a voltage level higher than the first voltage by a middle voltage, the middle voltage being generated in response to a first control signal, the first control signal being enabled during a time period in which the clock signal and a second control signal are disabled. The charge pumping unit boosts the second voltage to a third voltage, the third voltage being a voltage level higher than an input voltage by the first voltage, the input voltage being generated in response to the second control signal. The charge pump includes a first transfer unit to output the third voltage in response to the second control signal.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-youn Lee