Abstract: An electronic device including a semiconductor memory is provided to include a mat region comprising a plurality of memory cells, each including a second transistor; a first switching region located at a side of the mat region and including first transistors; and a second switching region located at the other side of the mat region and including third transistors, wherein the second transistors comprise: a plurality of second active regions; and a plurality of second gate structures extending in the first direction to cross the second active regions, wherein each second active regions is divided into a first side portion, a middle portion and a second side portion that are arranged alternately and repeatedly in the first direction, wherein the first transistors and the third transistors include their active regions and gate structures which are arranged in the same manner as those of the second transistors.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.

Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

Abstract: An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.

Abstract: An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction.

Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.

Abstract: An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a global line pair including a global bit line and a global source line; a plurality of cell matrices coupled between the global bit line and the global source line, each cell matrix including a plurality of local line pairs and a plurality of storage cells that are coupled to the plurality of local line pairs, wherein each storage cell is operable to store data and is coupled between local lines of a corresponding local line pair; and a plurality of isolation switch pairs that couple the plurality of cell matrices to the global bit line and the global source line of the global line pair, one isolation switch pair per cell matrix.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a global line pair including a global bit line and a global source line; a plurality of cell matrices coupled between the global bit line and the global source line, each cell matrix including a plurality of local line pairs and a plurality of storage cells that are coupled to the plurality of local line pairs, wherein each storage cell is operable to store data and is coupled between local lines of a corresponding local line pair; and a plurality of isolation switch pairs that couple the plurality of cell matrices to the global bit line and the global source line of the global line pair, one isolation switch pair per cell matrix.

Abstract: In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.

Abstract: An electronic device including a semiconductor memory is provided to include a mat region comprising a plurality of memory cells, each including a second transistor; a first switching region located at a side of the mat region and including first transistors; and a second switching region located at the other side of the mat region and including third transistors, wherein the second transistors comprise: a plurality of second active regions; and a plurality of second gate structures extending in the first direction to cross the second active regions, wherein each second active regions is divided into a first side portion, a middle portion and a second side portion that are arranged alternately and repeatedly in the first direction, wherein the first transistors and the third transistors include their active regions and gate structures which are arranged in the same manner as those of the second transistors.

Abstract: Devices and methods based on disclosed technology include, among others, an electronic device capable of improving a signal transfer characteristic and a method for fabricating the same. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate, open parts formed in the substrate on both sides of the buried gate, isolation layers each formed between a sidewall of the open part and a sidewall of the buried gate, source/drain regions formed in the substrate under the respective open parts, and contact plugs buried in the respective open parts.

Abstract: An electronic device includes a semiconductor device that includes: a substrate including a switching element having a buried gate electrode; a buried decoupling capacitor having a line width same as a line width of the buried gate electrode; and a variable resistance element, electrically coupled to the switching element, formed over the substrate.

Abstract: This patent document relates to memory circuits or devices and their applications in electronic devices or systems. The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device in which an electronic device capable of reducing an area, improving device characteristics due to a reduction in the resistance of a switching transistor, simplifying the process, and reducing a cost is provided. In accordance with the electronic device of this patent document, an area can be reduced, device characteristics can be improved due to a reduction in the resistance of the switching transistor, the process can be simplified, and a cost can be reduced.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.

Abstract: An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction.

Abstract: A nonvolatile memory apparatus includes: a memory cell coupled to a bit line and a source line; a word line configured to select the memory cell; and a local switch block configured to apply a write voltage, a read voltage, and a source line voltage to the bit line and the source line in response to a local switch select signal. In a write or read operation of the nonvolatile memory apparatus, the word line has a first voltage level, and the local switch select signal has a second voltage level higher than the first voltage level.

Abstract: In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar. array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.