Abstract: An electronic device includes a communication circuit, a speaker, and a processor. The processor is configured to identify a bitrate of a first audio bitstream received via the communication circuit from an external electronic device. The processor is configured to obtain, in response to the bitrate lower than a reference value, an audio signal by executing a bandwidth extension (BWE) for the first audio bitstream based on at least one coding parameter obtained from a second audio bitstream previously received via the communication circuit from the external electronic device before the first audio bitstream. The processor is configured to obtain, in response to the bitrate higher than or equal to the reference value, the audio signal for the first audio bitstream without executing the BWE. The processor is configured to output, based on the audio signal, audio via the speaker.

Abstract: A wearable electronic device according to an embodiment may comprise a plurality of speakers, a plurality of vibration devices, and at least one processor. The at least one processor may be configured to identify a first object corresponding to a first sound and a position of the first object in a virtual space of VR content displayed through the display. The at least one processor may be configured to obtain a second sound corresponding to the movement of the first object based on the first sound and the position of the first object. The at least one processor may be configured to output the second sound through the plurality of speakers. The at least one processor may be configured to determine one or more vibration devices corresponding to the movement of the first object among the plurality of vibration devices. The at least one processor may be configured to control the one or more vibration devices to vibrate while the second sound is output through the plurality of speakers.

Abstract: A pixel of a vision sensor includes a photoelectric converter configured to convert an optical signal into a current, a current-to-voltage converter configured to convert the current into a first voltage, an amplifier configured to generate an output voltage by amplifying a voltage level of the first voltage, at least one comparator configured to identify whether an event occurs based on comparing the output voltage with at least one threshold voltage, and generate an event signal based on identifying that the event occurs, and at least one counter configured to receive the event signal from the at least one comparator, obtain a count value by counting the event signal as information about an amount of change in illumination, and transmit output data comprising the count value.

Abstract: A positive active material includes a first positive active material including a lithium nickel-based composite oxide and including secondary particles in which a plurality of primary particles are aggregated, and a cobalt coating portion on a surface of the secondary particles; and a second positive active material including a lithium nickel-based composite oxide and including single particles and a cobalt coating portion on a surface of the single particles, wherein the surface of the single particles includes a high-concentration coating region having a cobalt content of greater than or equal to about 30 at % and a low-concentration coating region having a cobalt content of less than or equal to about 25 at % based on the total amount of nickel and cobalt, and a difference between the cobalt content in the high-concentration coating region and a cobalt content in the low-concentration coating region is about 20 at % to about 50 at %.

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Abstract: A neural array may include an array unit, a first processing unit, and a second processing unit. The array unit may include synaptic devices. The first processing unit may input a row input signal to the array unit, and receive a row output signal from the array unit. The second processing unit may input a column input signal to the array unit, and receive a column output signal from the array unit. The array unit may have a first array value and a second array value. When the first processing unit or the second processing unit receives an output signal based on the first array value from the array unit which has selected the first array value and then the array unit selects the second array value, it may input a signal generated based on the output signal to the array unit which has selected the second array value.

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

Abstract: A neuron device may include an input unit, a synapse unit, and an output unit. The synapse unit can be connected with the input unit and may include one or more synapse modules. Each of the one or more synapse modules may include multiple synapse elements connected in series and may be configured to operate in a time division multiplexing mode. Each synapse element may have specific coefficient information. In each of the one or more synapse modules, one of the multiple synapse elements connected in series may be configured to apply coefficient information to one of the multiple input signals received by the input unit. The output unit may obtain a weighted sum of the multiple input signals and may generate an output signal based on the weighted sum.

Abstract: A circuit module includes a model circuit and a look-up table (LUT). The model circuit generates an output signal based on one or more input signals, and corresponds to a digital circuit. The LUT stores one or more control signals and one or more operation parameters that are to be used to implement the model circuit. The one or more control signals and the one or more operation parameters correspond to an index determined by a combination of the one or more input signals and the output signal.

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Abstract: A circuit module includes a model circuit and a look-up table (LUT). The model circuit generates an output signal based on one or more input signals, and corresponds to a digital circuit. The LUT stores one or more control signals and one or more operation parameters that are to be used to implement the model circuit. The one or more control signals and the one or more operation parameters correspond to an index determined by a combination of the one or more input signals and the output signal.

Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.