Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data.

Abstract: A method of simulating an output of a nonlinear system modeling the output of the nonlinear system with a set of differential equations, the set of differential equations being expressed with a combination of first order to n-th order output responses, and an input signal with coefficients thereof, updating the coefficients of the first order to n-th order output responses when the coefficients of the input signal change to obtain the first order to n-th order output responses, and obtaining the output of the nonlinear system by summing the firstfirst order to n-th order output responses.

Abstract: A power supply and a gate driver includes a power switching element to control current, a control circuit to output a control signal for opening or closing of the power switching element, and a gate drive circuit to open or close the power switching element in accordance with the control signal. The gate drive circuit includes a first inductive circuit connected to a supply voltage source, and a second inductive circuit connected to an input stage of the power switching element, and transfers electrical energy stored in the input stage of the power switching element, using the first and second inductive circuits. Accordingly, electrical energy supplied to the input stage of the power switching element during an ON state of the power switching element is again recovered during an OFF state of the power switching element.

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Abstract: An integrated circuit in a PET imaging system with a plurality of photo detectors is provided. A plurality of differential transimpedance amplifiers with differential inputs and differential outputs is provided, wherein differential inputs for each differential transimpedance amplifier of the plurality of differential transimpedance amplifiers are electrically connected to a photodetector.

Abstract: A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.

Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data.

Abstract: A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.

Abstract: A method of adjusting a voltage supply to an electronic device coupled to a wired communication link in accordance with a performance metric associated with the wired communication link. A voltage adjust signal is generated based on the performance metric. The voltage adjustment signal is then used for updating the voltage supply to the electronic device.

Abstract: A method of adjusting a voltage supply to an electronic device coupled to a wired communication link in accordance with a performance metric associated with the wired communication link. A voltage adjust signal is generated based on the performance metric. The voltage adjustment signal is then used for updating the voltage supply to the electronic device.

Abstract: A clock-signal generator (e.g. a PLL or a DLL) uses non-volatile memory to store an analog control voltage that determines an output phase and/or frequency of the clock-signal generator. Locked loops take time to lock on a given reference frequency. To keep this time to a minimum, NVM 105 stores the control voltage during periods of inactivity, such as when the signal generator is powered down or in a standby mode. Non-volatile memory stores control voltages during operation in other embodiments to relax the area requirements otherwise required for integration capacitors to store phase and frequency information.

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Abstract: A differential signal receiver 106 implements intra-pair skew compensation for improving data transfer on a differential channel. In an embodiment, the receiver implements sampling by—multiple clocks with different phases such that the signals of the differential channel may be separately or individually time adjusted to account for skew between them so that they may be differentially compared for data resolution. In one embodiment, a positive sampler and negative sampler are controlled by distinct clock signals to permit, at different times, sampling and holding of the positive and negative signals representing a data bit on the differential channel. A differential decision circuit may then differentially resolve the data using a latter one of the distinct clock signals. Timing generation circuitry for producing the offset clocks may include a skew detector that permits dynamic adjustment of the different clock signals according to skew associated with the signals of the differential channel.

Abstract: A method of adjusting a voltage supply to an electronic device coupled to a wired communication link in accordance with a performance metric associated with the wired communication link. A voltage adjust signal is generated based on the performance metric. The voltage adjustment signal is then used for updating the voltage supply to the electronic device.

Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Abstract: A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., —the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

Abstract: A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. A charge pump system is coupled with the phase detector, including (1) a charge pump responsive to assertion of actuating signals from the UP output and the DOWN output to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust a bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.

Abstract: A method for simulating a system without a time invariant or periodically time-varying steady state is provided. The method limits the number of states included in a Markov chain model by discretizing the states based on Gaussian decomposition, utilizes a state exploration algorithm that discovers only recurrent states, and/or utilizes a state truncation algorithm that eliminates states with negligible stationary probabilities.