Patents by Inventor Jaeha Kim
Jaeha Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10432389Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.Type: GrantFiled: April 10, 2018Date of Patent: October 1, 2019Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Brian Leibowitz, Jaeha Kim, Jafar Savoj
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Patent number: 10397028Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.Type: GrantFiled: April 27, 2017Date of Patent: August 27, 2019Assignee: Rambus Inc.Inventors: Brian S. Leibowitz, Jaeha Kim
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Publication number: 20180323951Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.Type: ApplicationFiled: April 10, 2018Publication date: November 8, 2018Inventors: Hae-Chang Lee, Brian Leibowitz, Jaeha Kim, Jafar Savoj
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Publication number: 20180300611Abstract: A neuron device is generally described. One exemplary neuron device may include an input unit, a synapse unit, and an output unit. The input unit can be configured to receive multiple input signals. The synapse unit can be connected with the input unit and may include one or more synapse modules. Each of the one or more synapse modules may include multiple synapse elements connected in series and may be configured to operate in a time division multiplexing mode. Each synapse element may include a floating gate metal oxide silicon field effect transistor (MOSFET) and may have specific coefficient information. In each of the one or more synapse modules, one of the multiple synapse elements connected in series may be configured to apply coefficient information to one of the multiple input signals received by the input unit. The output unit may obtain a weighted sum of the multiple input signals to which the coefficient information is applied and may generate an output signal based on the weighted sum.Type: ApplicationFiled: October 1, 2015Publication date: October 18, 2018Inventors: Jaeha KIM, Yunju CHOI, Joonseok YANG, Seungheon BAEK
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Patent number: 10082875Abstract: An apparatus for generating tactile stimulation includes vibration actuators disposed on opposing sides of a finger, and a sensor configured to detect a position and a pointing direction of the finger, wherein the vibration actuators apply vibration to the finger with intensity and duration determined by the position and the pointing direction of the finger detected by the sensor, and wherein illusory stimulation is generated within the finger by the vibration generated by the vibration actuators.Type: GrantFiled: August 25, 2017Date of Patent: September 25, 2018Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Jaeha Kim, Jaeyoung Park, Yonghwan Oh
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Patent number: 9973328Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.Type: GrantFiled: July 13, 2016Date of Patent: May 15, 2018Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Brian Leibowitz, Jaeha Kim, Jafar Savoj
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Publication number: 20180121790Abstract: A neural array may include an array unit, a first processing unit, and a second processing unit. The array unit may include synaptic devices. The first processing unit may input a row input signal to the array unit, and receive a row output signal from the array unit. The second processing unit may input a column input signal to the array unit, and receive a column output signal from the array unit. The array unit may have a first array value and a second array value. When the first processing unit or the second processing unit receives an output signal based on the first array value from the array unit which has selected the first array value and then the array unit selects the second array value, it may input a signal generated based on the output signal to the array unit which has selected the second array value.Type: ApplicationFiled: December 27, 2017Publication date: May 3, 2018Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Jaeha KIM, Yunju CHOI, Seungheon BAEK
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Publication number: 20180052194Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.Type: ApplicationFiled: September 8, 2017Publication date: February 22, 2018Inventors: Hae-Chang Lee, Jaeha Kim, Brian Liebowitz
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Patent number: 9791492Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.Type: GrantFiled: July 13, 2016Date of Patent: October 17, 2017Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Jaeha Kim, Brian Liebowitz
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Publication number: 20170295040Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.Type: ApplicationFiled: April 27, 2017Publication date: October 12, 2017Inventors: Brian S. Leibowitz, Jaeha Kim
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Patent number: 9698666Abstract: A power supply and a gate driver includes a power switching element to control current, a control circuit to output a control signal for opening or closing of the power switching element, and a gate drive circuit to open or close the power switching element in accordance with the control signal. The gate drive circuit includes a first inductive circuit connected to a supply voltage source, and a second inductive circuit connected to an input stage of the power switching element, and transfers electrical energy stored in the input stage of the power switching element, using the first and second inductive circuits. Accordingly, electrical energy supplied to the input stage of the power switching element during an ON state of the power switching element is again recovered during an OFF state of the power switching element.Type: GrantFiled: December 9, 2014Date of Patent: July 4, 2017Assignees: SAMSUNG ELECTRONICS CO., LTD., SNU R&DB FOUNDATIONInventors: Jong Hyun Shin, Jaeha Kim, Hyun Soo Park, Jung-Ik Ha, Taewook Kang
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Patent number: 9660844Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.Type: GrantFiled: November 11, 2015Date of Patent: May 23, 2017Assignee: Rambus Inc.Inventors: Brian Leibowitz, Jaeha Kim
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Publication number: 20170099132Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.Type: ApplicationFiled: July 13, 2016Publication date: April 6, 2017Inventors: Hae-Chang Lee, Brian Leibowitz, Jaeha Kim, Jafar Savoj
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Publication number: 20170052221Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.Type: ApplicationFiled: July 13, 2016Publication date: February 23, 2017Inventors: Hae-Chang Lee, Jaeha Kim, Brian Liebowitz
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Patent number: 9491011Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data.Type: GrantFiled: July 31, 2014Date of Patent: November 8, 2016Assignee: Rambus Inc.Inventors: Jaeha Kim, Haechang Lee, Jung-Hoon Chun, Jared Zerbe
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Patent number: 9423441Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.Type: GrantFiled: September 17, 2012Date of Patent: August 23, 2016Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Jaeha Kim, Brian Leibowitz
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Patent number: 9419781Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.Type: GrantFiled: December 8, 2014Date of Patent: August 16, 2016Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Brian Leibowitz, Jaeha Kim, Jafar Savoj
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Publication number: 20160134442Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.Type: ApplicationFiled: November 11, 2015Publication date: May 12, 2016Inventors: Brian Leibowitz, Jaeha Kim
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Patent number: 9244179Abstract: An integrated circuit in a PET imaging system with a plurality of photo detectors is provided. A plurality of differential transimpedance amplifiers with differential inputs and differential outputs is provided, wherein differential inputs for each differential transimpedance amplifier of the plurality of differential transimpedance amplifiers are electrically connected to a photodetector.Type: GrantFiled: December 4, 2012Date of Patent: January 26, 2016Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Frances W. Y. Lau, Craig Steven Levin, Mark A. Horowitz, Hwang Ho Choi, Jaeha Kim
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Patent number: 9215112Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.Type: GrantFiled: November 24, 2010Date of Patent: December 15, 2015Assignee: Rambus Inc.Inventors: Brian S. Leibowitz, Jaeha Kim