Abstract: A semiconductor integrated circuit includes at least one second semiconductor chip configured to generate an internal voltage, and a first semiconductor chip including a monitoring unit configured to monitor the internal voltage, and a first pad configured to provide monitoring result information outputted from the monitoring unit to a test device.

Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.

Abstract: An integrated circuit includes a plurality of semiconductor devices. Each of the semiconductor devices includes an internal voltage generation unit configured to generate a plurality of internal voltages, a voltage select output unit configured to output a default voltage of a plurality of internal voltages to a preset pad in response to an initial value of a select code, and selectively output the other voltages of the plurality of internal voltages to the pad in response to variations of the select code, and a stack operation control unit configured to control the voltage select output unit to output the default voltage to the pad in response to a stack signal and a predetermined value of the select code, instead of the initial value of the select code, and whether or not to activate the stack signal is determined according to whether or not the plurality of semiconductor devices are stacked.

Abstract: A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.

Abstract: A semiconductor integrated circuit includes an internal reference voltage generation unit configured to generate an internal reference voltage; a high voltage generation unit configured to pump an external driving voltage based on the internal reference voltage applied from the internal reference voltage generation unit, and generate a high voltage having a specified level; and a reference voltage transfer unit configured to generate a test reference voltage from a reference voltage in a package test mode to correspond to a change in a driving operation of the external driving voltage applied from outside, and monitor and force the internal reference voltage.

Abstract: An integrated circuit includes a plurality of semiconductor devices. Each of the semiconductor devices includes an internal voltage generation unit configured to generate a plurality of internal voltages, a voltage select output unit configured to output a default voltage of a plurality of internal voltages to a preset pad in response to an initial value of a select code, and selectively output the other voltages of the plurality of internal voltages to the pad in response to variations of the select code, and a stack operation control unit configured to control the voltage select output unit to output the default voltage to the pad in response to a stack signal and a predetermined value of the select code, instead of the initial value of the select code, and whether or not to activate the stack signal is determined according to whether or not the plurality of semiconductor devices are stacked.

Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.

Abstract: A semiconductor apparatus includes: a master chip and at least one slave chip configured to be stacked one on top of another; and a through-silicon via (TSV) configured to penetrate and electrically couple the master chip and the at least one slave chip, wherein the at least one slave chip receives a reference voltage generated from the master chip via the TSV and independently trims the reference voltage and then generates an internal voltage with the trimmed reference voltage.

Abstract: A power-up signal generation circuit includes a power-up signal generator configured to enable a power-up signal when a level of an external power voltage is higher than a target level, and a target level controller configured to change the target level in response to a current consumption signal indicating a current consumption of a system including the power-up signal generation circuit.

Abstract: A semiconductor integrated circuit includes at least one second semiconductor chip configured to generate an internal voltage, and a first semiconductor chip including a monitoring unit configured to monitor the internal voltage, and a first pad configured to provide monitoring result information outputted from the monitoring unit to a test device.

Abstract: A semiconductor integrated circuit includes a fuse set; a terminal assigned to be applied with a first external signal in a normal operation; and a control unit configured to receive a second external signal through the terminal and apply the received second external signal to the fuse set in a fuse control operation.

Abstract: A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction.

Abstract: A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

Abstract: A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.

Abstract: A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction.

Abstract: A semiconductor integrated circuit includes a fuse set; a terminal assigned to be applied with a first external signal in a normal operation; and a control unit configured to receive a second external signal through the terminal and apply the received second external signal to the fuse set in a fuse control operation.

Abstract: A semiconductor apparatus includes: a master chip and at least one slave chip configured to be stacked one on top of another; and a through-silicon via (TSV) configured to penetrate and electrically couple the master chip and the at least one slave chip, wherein the at least one slave chip receives a reference voltage generated from the master chip via the TSV and independently trims the reference voltage and then generates an internal voltage with the trimmed reference voltage.

Abstract: Provided is a technology for monitoring the electrical resistance of an element such as a fuse whose resistance is changed due to the electrical stress among internal circuits included in a semiconductor device. The present invention provides a monitoring circuit to monitor the change in the device specification during the device is being programmed and after the device is programmed. The present invention enables the verification of an optimized condition to let the device have a certain electrical resistance, by comparing the load voltage and the fuse voltage with the reference voltage that can sense the range of resistance variation more precisely. Also, it can guarantee device reliability since it is still possible to sense electrical resistance after the electrical stress is being given. Also, the present invention can increase the utility of the fuse by possessing an output to monitor electrical resistance sensed inside of the semiconductor.

Abstract: A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.