Patents by Inventor Jagdish Narayan

Jagdish Narayan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070280848
    Abstract: Thin tantalum films having novel microstructures are provided. The films have microstructures such as nanocrystalline, single crystal and amorphous. These films provide excellent diffusion barrier properties and are useful in microelectronic devices. Methods of forming the films using pulsed laser deposition (PLD) and molecular beam epitaxy (MBE) deposition methods are also provided, as are microelectronic devices incorporating these films.
    Type: Application
    Filed: March 24, 2005
    Publication date: December 6, 2007
    Inventors: Jagdish Narayan, Prabhat Kumar, Richard Wu
  • Patent number: 7273733
    Abstract: The present invention describes a process for the isolation of polyhydroxybutyrate of the formula 1 by growing a culture of Bacillus mycoides RLJ B-017 in a growth medium and a carbon source selected from sucrose, molasses and pineapple waste.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: September 25, 2007
    Assignee: Council of Scientific and Industrial Research
    Inventors: Manobjyoti Bordoloi, Bornali Borah, Purbali S. Thakur, Jagdish Narayan Nigam
  • Publication number: 20060266442
    Abstract: Nanostructures and methods of making nanostructures having self-assembled nanodot arrays wherein nanodots are self-assembled in a matrix material due to the free energies of the nanodot material and/or differences in the Gibb's free energy of the nanodot materials and matrix materials.
    Type: Application
    Filed: August 4, 2006
    Publication date: November 30, 2006
    Inventors: Jagdish Narayan, Ashutosh Tiwari
  • Patent number: 7129068
    Abstract: The present invention describes a process for the isolation of polyhydroxybutyrate of the formula 1 by growing a culture of Bacillus mycoides RLJ B-017 in a growth medium and a carbon source selected from sucrose, molasses and pineapple waste.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: October 31, 2006
    Assignee: Council of Scientific and Industrial Research
    Inventors: Manobjyoti Bordoloi, Bornali Borah, Purbali S. Thakur, Jagdish Narayan Nigam
  • Patent number: 7122841
    Abstract: A semiconductor device includes a substrate having a first major surface; a semiconductor device structure over the first surface of the substrate, the device structure comprising an n-type semiconductor layer, and a p-type semiconductor layer over the n-type semiconductor layer; a p-side electrode having a first and a second surface, wherein the first surface is in electrical contact with the p-type semiconductor layer; and a p-side bonding pad over the p-side electrode. Preferably, the semiconductor device further comprises an n-side bonding pad over an n-type semiconductor layer. The p-side and n-side bonding pads each independently includes a gold layer as its top layer and a single or multiple layers of a diffusion barrier under the top gold layer. Optionally, one or more metal layers are further included under the diffusion barrier. Typically, the p-side bonding pad is formed on the p-side electrode.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: October 17, 2006
    Assignee: Kopin Corporation
    Inventors: Tchang-Hun Oh, Hong K. Choi, John C. C. Fan, Jagdish Narayan
  • Patent number: 7105118
    Abstract: Nanostructures and methods of making nanostructures having self-assembled nanodot arrays wherein nanodots are self-assembled in a matrix material due to the free energies of the nanodot material and/or differences in the Gibb's free energy of the nanodot materials and matrix materials.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: September 12, 2006
    Assignee: North Carolina State University
    Inventors: Jagdish Narayan, Ashutosh Tiwari
  • Publication number: 20060130745
    Abstract: A method of forming an epitaxial film on a substrate includes growing an initial layer of a film on a substrate at a temperature Tgrowth, said initial layer having a thickness h and annealing the initial layer of the film at a temperature Tanneal, thereby relaxing the initial layer, wherein said thickness h of the initial layer of the film is greater than a critical thickness hc. The method further includes growing additional layers of the epitaxial film on the initial layer subsequent to annealing. In some embodiments, the method further includes growing a layer of the film that includes at least one amorphous island.
    Type: Application
    Filed: February 10, 2006
    Publication date: June 22, 2006
    Inventor: Jagdish Narayan
  • Publication number: 20060016388
    Abstract: A method of forming an epitaxial film on a substrate includes growing an initial layer of a film on a substrate at a temperature Tgrowth, said initial layer having a thickness h and annealing the initial layer of the film at a temperature Tanneal, thereby relaxing the initial layer, wherein said thickness h of the initial layer of the film is greater than a critical thickness hc. The method further includes growing additional layers of the epitaxial film on the initial layer subsequent to annealing. In some embodiments, the method further includes growing a layer of the film that includes at least one amorphous island.
    Type: Application
    Filed: January 18, 2005
    Publication date: January 26, 2006
    Applicant: Kopin Corporation
    Inventor: Jagdish Narayan
  • Patent number: 6955985
    Abstract: A method of forming an epitaxial film on a substrate includes growing an initial layer of a film on a substrate at a temperature Tgrowth, said initial layer having a thickness h and annealing the initial layer of the film at a temperature Tanneal, thereby relaxing the initial layer, wherein said thickness h of the initial layer of the film is greater than a critical thickness hc. The method further includes growing additional layers of the epitaxial film on the initial layer subsequent to annealing. In some embodiments, the method further includes growing a layer of the film that includes at least one amorphous island.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: October 18, 2005
    Assignee: Kopin Corporation
    Inventor: Jagdish Narayan
  • Publication number: 20050161689
    Abstract: An optoelectronic device such as an LED or laser which produces spontaneous emission by recombination of carriers (electrons and holes) trapped in Quantum Confinement Regions formed by transverse thickness variations in Quantum Well layers of group III nitrides.
    Type: Application
    Filed: December 6, 2004
    Publication date: July 28, 2005
    Applicant: Kopin Corporation
    Inventors: Jagdish Narayan, Jinlin Ye, Schang-Jing Hon, Ken Fox, Jyh Chen, Hong Choi, John Fan
  • Publication number: 20050124161
    Abstract: Epitaxial gallium nitride is grown on a silicon substrate while reducing or suppressing the formation of a buffer layer. The gallium nitride may be grown directly on the silicon substrate, for example using domain epitaxy. Alternatively, less than one complete monolayer of silicon nitride may be formed between the silicon and the gallium nitride. Subsequent to formation of the gallium nitride, an interfacial layer of silicon nitride may be formed between the silicon and the gallium nitride.
    Type: Application
    Filed: October 21, 2004
    Publication date: June 9, 2005
    Inventors: Thomas Rawdanowicz, Jagdish Narayan
  • Patent number: 6881983
    Abstract: An optoelectronic device such as an LED or laser which produces spontaneous emission by recombination of carriers (electrons and holes) trapped in Quantum Confinement Regions formed by transverse thickness variations in Quantum Well layers of group III nitrides.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: April 19, 2005
    Assignee: Kopin Corporation
    Inventors: Jagdish Narayan, Jinlin Ye, Schang-Jing Hon, Ken Fox, Jyh Chia Chen, Hong K. Choi, John C. C. Fan
  • Patent number: 6847052
    Abstract: A semiconductor device includes: a substrate; an n-type semiconductor layer over the substrate, the n-type semiconductor layer having a planar top surface; a p-type semiconductor layer extending over a major portion of the n-type semiconductor layer and not extending over an exposed region of the n-type semiconductor layer located adjacent to at least one edge of the planar top surface of the n-type semiconductor layer; a first bonding pad provided on the exposed region of the n-type semiconductor layer; an electrode layer extending over the p-type semiconductor layer; and a second bonding pad on the electrode layer, the bonding pad including a central region for securing an electrical interconnect, and at least one finger-like region protruding from the central region, the finger-like region having a length extending away from the central region and a width that is substantially less than the length. A method for producing a semiconductor device also is described.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: January 25, 2005
    Assignee: Kopin Corporation
    Inventors: John C. C. Fan, Hong K. Choi, Tchang-Hun Oh, Jyh Chia Chen, Jagdish Narayan
  • Publication number: 20040262621
    Abstract: A semiconductor device includes a substrate having a first major surface; a semiconductor device structure over the first surface of the substrate, the device structure comprising an n-type semiconductor layer, and a p-type semiconductor layer over the n-type semiconductor layer; a p-side electrode having a first and a second surface, wherein the first surface is in electrical contact with the p-type semiconductor layer; and a p-side bonding pad over the p-side electrode. Preferably, the semiconductor device further comprises an n-side bonding pad over an n-type semiconductor layer. The p-side and n-side bonding pads each independently includes a gold layer as its top layer and a single or multiple layers of a diffusion barrier under the top gold layer. Optionally, one or more metal layers are further included under the diffusion barrier. Typically, the p-side bonding pad is formed on the p-side electrode.
    Type: Application
    Filed: June 3, 2004
    Publication date: December 30, 2004
    Applicant: Kopin Corporation
    Inventors: Tchang-hun Oh, Hong K. Choi, John C. C. Fan, Jagdish Narayan
  • Publication number: 20040191878
    Abstract: The present invention describes a process for the isolation of polyhydroybutyrate of the formula 1 1
    Type: Application
    Filed: July 3, 2003
    Publication date: September 30, 2004
    Applicant: COUNCIL OF SCIENTIFIC AND INDUSTRIAL RESEARCH
    Inventors: Manobjyoti Bordoloi, Bornali Borah, Purbali S. Thakur, Jagdish Narayan Nigam
  • Publication number: 20040119064
    Abstract: Nanostructures and methods of making nanostructures having self-assembled nanodot arrays wherein nanodots are self-assembled in a matrix material due to the free energies of the nanodot material and/or differences in the Gibb's free energy of the nanodot materials and matrix materials.
    Type: Application
    Filed: November 26, 2003
    Publication date: June 24, 2004
    Inventors: Jagdish Narayan, Ashutosh Tiwari
  • Patent number: 6734091
    Abstract: An improved electrode for a p-type gallium nitride based semiconductor material is disclosed that includes a layer of an oxidized metal and a first and a second layer of a metallic material. The electrode is formed by depositing three or more metallic layers over the p-type semiconductor layer such that at least one metallic layer is in contact with the p-type semiconductor layer. At least two of the metallic layers are then subjected to an annealing treatment in the presence of oxygen to oxidize at least one of the metallic layers to form a metal oxide. The electrodes provide good ohmic contacts to p-type gallium nitride-based semiconductor materials and, thus, lower the operating voltage of gallium nitride-based semiconductor devices.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: May 11, 2004
    Assignee: Kopin Corporation
    Inventors: Tchang-Hun Oh, Hong K. Choi, Bor-Yeu Tsaur, John C. C. Fan, Shirong Liao, Jagdish Narayan
  • Publication number: 20040077135
    Abstract: A semiconductor device includes: a substrate; an n-type semiconductor layer over the substrate, the n-type semiconductor layer having a planar top surface; a p-type semiconductor layer extending over a major portion of the n-type semiconductor layer and not extending over an exposed region of the n-type semiconductor layer located adjacent to at least one edge of the planar top surface of the n-type semiconductor layer; a first bonding pad provided on the exposed region of the n-type semiconductor layer; an electrode layer extending over the p-type semiconductor layer; and a second bonding pad on the electrode layer, the bonding pad including a central region for securing an electrical interconnect, and at least one finger-like region protruding from the central region, the finger-like region having a length extending away from the central region and a width that is substantially less than the length. A method for producing a semiconductor device also is described.
    Type: Application
    Filed: June 17, 2003
    Publication date: April 22, 2004
    Applicant: Kopin Corporation
    Inventors: John C.C. Fan, Hong K. Choi, Tchang-Hun Oh, Jyh Chia Chen, Jagdish Narayan
  • Publication number: 20040072381
    Abstract: A method of forming an epitaxial film on a substrate includes growing an initial layer of a film on a substrate at a temperature Tgrowth, said initial layer having a thickness h and annealing the initial layer of the film at a temperature Tanneal, thereby relaxing the initial layer, wherein said thickness h of the initial layer of the film is greater than a critical thickness hc. The method further includes growing additional layers of the epitaxial film on the initial layer subsequent to annealing. In some embodiments, the method further includes growing a layer of the film that includes at least one amorphous island.
    Type: Application
    Filed: June 27, 2003
    Publication date: April 15, 2004
    Applicant: Kopin Corporation
    Inventor: Jagdish Narayan
  • Publication number: 20040000671
    Abstract: An improved electrode for a p-type gallium nitride based semiconductor material is disclosed that includes a layer of an oxidized metal and a first and a second layer of a metallic material. The electrode is formed by depositing three or more metallic layers over the p-type semiconductor layer such that at least one metallic layer is in contact with the p-type semiconductor layer. At least two of the metallic layers are then subjected to an annealing treatment in the presence of oxygen to oxidize at least one of the metallic layers to form a metal oxide. The electrodes provide good ohmic contacts to p-type gallium nitride-based semiconductor materials and, thus, lower the operating voltage of gallium nitride-based semiconductor devices.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 1, 2004
    Applicant: Kopin Corporation
    Inventors: Tchang-Hun Oh, Hong K. Choi, Bor-Yeu Tsaur, John C.C. Fan, Shirong Liao, Jagdish Narayan